公开(公告)号：US20230368745A1

公开(公告)日：2023-11-16

申请号：US18354751

申请日：2023-07-19

Applicant: Japan Display Inc.

Inventor： Takehiro SHIMA

IPC: G09G3/36 ,  G02F1/1345 ,  G02F1/1362 ,  G09G3/20

CPC classification number: G09G3/3611 ,  G02F1/13454 ,  G02F1/1362 ,  G09G3/20 ,  G09G3/3648 ,  G09G2300/04 ,  G09G2310/0291 ,  G11C11/41

Abstract: According to one embodiment, a display device includes a pair of substrates including a display area in which pixels are arranged, pixel electrodes and memories provided in the pixels, signal lines supplied with digital signals, switching elements connecting the memories and the signal lines, scanning lines supplied with scanning signals, a first driver unit, and a second driver unit. The first driver unit is provided in a peripheral area around the display area, and supplies the digital signal to the signal line. The second driver unit is provided in the peripheral area, and supplies the scanning signal to the scanning line. In the display device, at least a part of the first driver unit is provided between the display area and the second driver unit.

公开(公告)号：US20190139600A1

公开(公告)日：2019-05-09

申请号：US16241717

申请日：2019-01-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Cheng WU ,  Wei Min CHAN ,  Yen-Huei CHEN ,  Hung-Jen LIAO ,  Ping-Wei WANG

IPC: G11C11/419 ,  G11C11/412 ,  G11C11/4063 ,  G11C11/409 ,  G11C11/41

CPC classification number: G11C11/419 ,  G11C11/4063 ,  G11C11/409 ,  G11C11/41 ,  G11C11/412

Abstract: A static random access memory (SRAM) includes a bit cell that includes a p-type pass gate, a bit information path connected to the bit cell by the p-type pass gate, and a write multiplexer connected to the bit information path. The write multiplexer includes a p-type transistor configured to selectively couple the bit information path to a flip-flop.

公开(公告)号：US20190122715A1

公开(公告)日：2019-04-25

申请号：US15793046

申请日：2017-10-25

Applicant: Qualcomm Incorporated

Inventor： Peter RATHFELDER

IPC: G11C8/20 ,  G06F12/14 ,  H01L21/822 ,  G11C11/41 ,  H01L23/00 ,  H01L31/048

CPC classification number: G11C8/20 ,  G06F12/1425 ,  G06F21/87 ,  G11C11/41 ,  H01L21/822 ,  H01L23/576 ,  H01L31/048

Abstract: An integrated circuit includes a substrate, a first circuit disposed on the substrate, a photoelectric cell disposed on the substrate and coupled to the first circuit, the photoelectric cell to provide power to the first circuit when the photoelectric cell is exposed to light, and the first circuit to allow disabling at least a portion of the integrated circuit when powered by the photoelectric cell.

公开(公告)号：US10056389B2

公开(公告)日：2018-08-21

申请号：US15011396

申请日：2016-01-29

Applicant: Kilopass Technology, Inc.

Inventor： Harry Luan ,  Bruce L. Bateman ,  Valery Axelrad ,  Charlie Cheng ,  Christophe J. Chevallier

IPC: H01L27/11 ,  H01L21/8229 ,  H01L21/8249 ,  H01L27/102 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/732 ,  H01L29/74 ,  G11C11/39 ,  H01L29/745 ,  G11C11/41 ,  H01L27/06 ,  H01L27/082 ,  G11C11/411

CPC classification number: H01L27/1104 ,  G11C11/39 ,  G11C11/41 ,  G11C11/411 ,  H01L21/8229 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0821 ,  H01L27/0826 ,  H01L27/1025 ,  H01L27/1027 ,  H01L27/11 ,  H01L27/1116 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/083 ,  H01L29/0847 ,  H01L29/1004 ,  H01L29/1012 ,  H01L29/1095 ,  H01L29/66272 ,  H01L29/66386 ,  H01L29/732 ,  H01L29/742 ,  H01L29/7455

Abstract: A memory cell based upon thyristors for an SRAM integrated circuit can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM cells. Special circuitry provides lowered power consumption during standby.

公开(公告)号：US10051265B2

公开(公告)日：2018-08-14

申请号：US13963015

申请日：2013-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-jung Kim ,  U-in Chung ,  Hyun-sik Choi

IPC: H04N7/12 ,  H04N11/02 ,  H04N11/04 ,  H04N19/593 ,  G11C14/00 ,  H03K19/177 ,  G11C11/41 ,  G11C29/02

CPC classification number: H04N19/50 ,  G11C11/41 ,  G11C14/009 ,  G11C29/028 ,  H03K19/17748 ,  H03K19/17772 ,  H03K19/17776 ,  H04N19/17

Abstract: A logic device includes: a function block and a configuration block. The function block is configurable to perform operations associated with a plurality of operation modes. The configuration block is configured to configure the function block to perform an operation associated with any one of the plurality of operation modes. The logic device also includes a controller configured to control the configuration block so that the function block is configured to perform the operation.

公开(公告)号：US09953925B2

公开(公告)日：2018-04-24

申请号：US14975830

申请日：2015-12-20

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Zeev Wurman

IPC: H01L23/528 ,  H01L27/06 ,  H01L23/544 ,  B82Y10/00 ,  G11C16/04 ,  G11C16/10 ,  H01L21/84 ,  H01L21/683 ,  H01L21/762 ,  H01L27/02 ,  H01L29/78 ,  H01L27/092 ,  H01L27/105 ,  H01L27/108 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792 ,  H01L27/11 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/118 ,  H01L27/12 ,  H01L29/10 ,  G11C11/41 ,  G11C17/18 ,  G11C29/32 ,  G11C29/44 ,  H01L23/00 ,  H01L29/66 ,  H01L27/088 ,  H01L23/36

CPC classification number: H01L23/5286 ,  B82Y10/00 ,  G11C11/41 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/10 ,  G11C17/18 ,  G11C29/32 ,  G11C29/44 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/84 ,  H01L23/36 ,  H01L23/544 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/0694 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1052 ,  H01L27/10802 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/1203 ,  H01L29/1033 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/78696 ,  H01L29/7881 ,  H01L29/792 ,  H01L2221/6835 ,  H01L2221/68381 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81001 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2924/014 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A 3D IC device including: a first semiconductor layer including first mono-crystallized transistors, where the first mono-crystallized transistors are interconnected by at least one metal layer including aluminum or copper; a second layer including second mono-crystallized transistors and overlaying the at least one metal layer, where the at least one metal layer is in-between the first semiconductor layer and the second layer; a global power grid to distribute power to the device overlaying the second layer; and a local power grid to distribute power to the first mono-crystallized transistors, where the global power grid is connected to the local power grid by a plurality of through second layer vias, and where the vias have a radius of less than 150 nm.

公开(公告)号：US09899389B2

公开(公告)日：2018-02-20

申请号：US15426588

申请日：2017-02-07

Applicant: Kilopass Technology, Inc.

Inventor： Harry Luan ,  Bruce L. Bateman ,  Valery Axelrad ,  Charlie Cheng ,  Christophe J. Chevallier

IPC: H01L27/102 ,  H01L21/8249 ,  H01L29/74

CPC classification number: H01L27/1025 ,  G11C11/39 ,  G11C11/41 ,  G11C11/411 ,  G11C11/412 ,  G11C11/419 ,  H01L21/76229 ,  H01L21/768 ,  H01L21/8229 ,  H01L21/8249 ,  H01L23/528 ,  H01L27/0623 ,  H01L27/0821 ,  H01L27/0826 ,  H01L27/1027 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/083 ,  H01L29/1004 ,  H01L29/1012 ,  H01L29/1095 ,  H01L29/42304 ,  H01L29/6625 ,  H01L29/66272 ,  H01L29/735 ,  H01L29/737 ,  H01L29/7436 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.

公开(公告)号：US09741413B2

公开(公告)日：2017-08-22

申请号：US15216652

申请日：2016-07-21

Applicant: Kilopass Technology, Inc.

Inventor： Harry Luan ,  Bruce L. Bateman ,  Valery Axelrad ,  Charlie Cheng

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/39 ,  G11C11/418 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/102 ,  H01L27/11 ,  G11C5/14 ,  G11C11/41 ,  G11C11/411 ,  G11C11/416 ,  H01L27/082

CPC classification number: G11C11/00 ,  G11C5/148 ,  G11C11/39 ,  G11C11/41 ,  G11C11/411 ,  G11C11/4113 ,  G11C11/416 ,  G11C11/418 ,  G11C11/419 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0821 ,  H01L27/0826 ,  H01L27/1027 ,  H01L27/1104 ,  H01L29/7404

Abstract: A six-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with methods of operation. Methods of increasing the operational speed in reading the contents of a selected memory cell in an array of such memory cells while lowering power consumption, and of avoiding an indeterminate memory cell state when a memory cell is “awakened” from Standby are described.

公开(公告)号：US09728248B2

公开(公告)日：2017-08-08

申请号：US14657914

申请日：2015-03-13

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G11C11/41 ,  G11C11/412 ,  G11C14/00 ,  G11C16/04 ,  H01L27/11

CPC classification number: G11C11/41 ,  G11C11/4125 ,  G11C14/0054 ,  G11C14/0063 ,  G11C16/0416 ,  H01L23/5226 ,  H01L27/1104 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/518 ,  H01L29/788

Abstract: A semiconductor structure includes first and second source/drain region disposed in a semiconductor body and spaced from each other by a channel region. A gate electrode overlies the channel region and a capacitor electrode is disposed between the gate electrode and the channel region. A first gate dielectric is disposed between the gate electrode and the capacitor electrode and a second gate dielectric disposed between the capacitor electrode and the channel region. A first electrically conductive contact region is in electrical contact with the gate electrode and a second electrically conductive contact region in electrical contact with the capacitor electrode. The first and second contact regions are electrically isolated from one another.

公开(公告)号：US09689919B2

公开(公告)日：2017-06-27

申请号：US14556228

申请日：2014-11-30

Applicant: Yunwu Zhao ,  Hao Wang

Inventor： Yunwu Zhao ,  Hao Wang

IPC: G11C29/00 ,  G01R31/30 ,  G01R31/3177 ,  G11C29/26 ,  G11C29/50 ,  G11C11/41

CPC classification number: G01R31/3177 ,  G11C11/41 ,  G11C29/26 ,  G11C29/50016

Abstract: In an integrated circuit, a first scan chain of flip-flops is loaded with data for testing data retention of the flip-flops and a memory is loaded with data for performing a retention test by a memory built-in self-test (MBIST) wrapper circuit. A portion of the system is placed in a low-power state for a predetermined period of time before data is read from the memory and retention of data by the memory while in the low-power state is determined.