公开(公告)号：US07120169B2

公开(公告)日：2006-10-10

申请号：US10022893

申请日：2001-12-20

Applicant: Michael Joachim Wolf ,  Werner Beisel

Inventor： Michael Joachim Wolf ,  Werner Beisel

IPC: H04J3/06 ,  H04L12/28

CPC classification number: H04Q11/0005 ,  H04J3/0632 ,  H04J3/1611 ,  H04L12/56 ,  H04L47/283 ,  H04Q2011/0045

Abstract: A network device (NWE) for a digital transmission network with synchronous digital hierarchy receives data steams containing frames with data packets mapped therein and addressed by a phase reference identifier. Internally, the network device has redundant transfer paths which potentially cause different delay. The network element compensates for that delay by adjusting the phase reference identifier allocated to a respective data packet by a predetermined phase correcting value, leading in the phase, which corresponds to a maximum expected delay for transfer of the data packets on internal transfer paths, and by buffering the data packet by a buffering time such that its buffering time and its delay actually needed for passing through the network device in total correspond to the maximum expected delay taken into account by the phase adjustment.

公开(公告)号：US5214638A

公开(公告)日：1993-05-25

申请号：US610524

申请日：1990-11-08

Applicant: Albert Norz ,  Albrecht Schaffert ,  Werner Beisel ,  Kalman Szechenyi

Inventor： Albert Norz ,  Albrecht Schaffert ,  Werner Beisel ,  Kalman Szechenyi

IPC: H04L12/20 ,  H04Q11/04

CPC classification number: H04Q11/04

Abstract: The network access node of a digital communication system for the bidirectional transmission of message signals between, for example, a switching center and subscribers as an electrically switchable connection between the lines to the switching centers with a first interface and the lines to the subscribers with a second interface. The first interface is preferably an interface for a time-division multiplex signal with a transmission rate of 2 Mbit/s; the second interface is preferably an interface for signals in multiple access with time-division multiplex (TDM/TDMA). The buffer memory of the TDM/TDMA system is made up of partial memories arranged as a matrix. The partial memories are used simultaneously as a buffer memory for the circuit of the paths.

Abstract translation: 数字通信系统的网络接入节点，用于在诸如交换中心和用户之间的消息信号的双向传输之间，作为具有第一接口的交换中心的线路之间的电可切换连接，以及具有用户 第二个接口 第一接口优选地是用于具有2Mbit / s的传输速率的时分复用信号的接口; 第二接口优选地是用于具有时分复用（TDM / TDMA）的多路访问中的信号的接口。 TDM / TDMA系统的缓冲存储器由作为矩阵排列的部分存储器构成。 部分存储器同时用作路径电路的缓冲存储器。