公开(公告)号：US20230289088A1

公开(公告)日：2023-09-14

申请号：US17654552

申请日：2022-03-11

Applicant: Micron Technology, Inc.

Inventor： Caixia Yang ,  Deping He

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G06F3/0676

Abstract: Methods, systems, and devices for suspension during a multi-plane write procedure are described. A memory system may perform a multi-plane write procedure by writing to a set of planes in parallel. Upon detecting a defective plane in the set of planes, the memory system may suspend writing to the defective plane until writing to the other planes in the set of planes is finished. The memory system may then resume writing to the defective plane.

公开(公告)号：US20240393977A1

公开(公告)日：2024-11-28

申请号：US18636584

申请日：2024-04-16

Applicant: Micron Technology, Inc.

Inventor： Ratna Priyanka Sistla ,  Dan Xu ,  Tomoko Ogura Iwasaki ,  Caixia Yang ,  Lee-eun Yu

IPC: G06F3/06

Abstract: A memory device includes a memory array configured as quad-level cell (QLC) memory and a control logic operatively coupled to the memory array. The control logic identifies a first two bits of particular pages of a QLC logical state. The control logic causes memory cells of the memory array to be coarse programmed with a threshold voltage distribution of a multi-level cell (MLC) logical state corresponding to the first two bits. The control logic reads the MLC logical state from the memory cells and a second two bits from a cache buffer to determine the QLC logical state. The control logic causes the memory cells to be further coarse programmed with a QLC threshold voltage distribution corresponding to the QLC logical state.

公开(公告)号：US12099734B2

公开(公告)日：2024-09-24

申请号：US17846761

申请日：2022-06-22

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Bo Zhou ,  Caixia Yang

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02

CPC classification number: G06F3/064 ,  G06F3/061 ,  G06F3/0679 ,  G06F12/0246

Abstract: Methods, systems, and devices for memory block utilization in memory systems are described. A system configured to allow a memory device to group or segment a memory block into two or more sub-memory blocks, which can be independently programmed is described herein. For example, a host system may determine a configuration of a memory array, and communicate the configuration information to the memory system, and transmit a command for an operation to the memory system. In some examples, the memory system may utilize the memory array configuration information and determine to segment the blocks of memory cells into sub-blocks. By segmenting the memory block into sub-blocks, the memory device may maintain its memory block density while supporting efficient programming of blocks of the memory array.

公开(公告)号：US20240069733A1

公开(公告)日：2024-02-29

申请号：US18233433

申请日：2023-08-14

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Caixia Yang

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0679

Abstract: A memory sub-system to initiate an erase operation to erase a first set of memory cells of a first memory block and a second set of memory cells of a second memory block of a memory device. One or more erase pulses of the erase operation are caused to be applied to the first set of memory cells of the first memory block and the second set of memory cells of the second memory block concurrently. A first erase verify sub-operation of the erase operation is caused to be performed to verify the first memory block is erased and a second erase verify sub-operation of the erase operation is caused to be performed to verify the second memory block is erased.