公开(公告)号：US20140021550A1

公开(公告)日：2014-01-23

申请号：US14032541

申请日：2013-09-20

Applicant: Micron Technology, Inc.

Inventor： Fernando Gonzalez

IPC: H01L27/108

CPC classification number: H01L27/10802 ,  H01L21/823468 ,  H01L21/84 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841

Abstract: This invention includes a capacitorless one transistor DRAM cell that includes a pair of spaced source/drain regions received within semiconductive material. An electrically floating body region is disposed between the source/drain regions within the semiconductive material. A first gate spaced is apart from and capacitively coupled to the body region between the source/drain regions. A pair of opposing conductively interconnected second gates are spaced from and received laterally outward of the first gate. The second gates are spaced from and capacitively coupled to the body region laterally outward of the first gate and between the pair of source/drain regions. Methods of forming lines of capacitorless one transistor DRAM cells are disclosed.

Abstract translation: 本发明包括一个无电容的一晶体管DRAM单元，其包括在半导体材料内接收的一对间隔的源/漏区。 电浮动体区域设置在半导体材料内的源极/漏极区域之间。 间隔开的第一栅极与电源/漏极区域之间的体区分开并电容耦合。 一对相对的导电互连的第二栅极与第一栅极间隔开并横向向外延伸。 第二栅极与第一栅极的横向外侧和一对源极/漏极区之间的体区间隔开并电容耦合。 公开了形成无电容的一个晶体管DRAM单元的线的方法。