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    CAPACITOR-LESS MEMORY CELL, DEVICE, SYSTEM AND METHOD OF MAKING SAME
    1.
    发明申请
    CAPACITOR-LESS MEMORY CELL, DEVICE, SYSTEM AND METHOD OF MAKING SAME 有权
    无电容器存储器单元，器件，系统及其制造方法

    公开(公告)号：US20130252390A1

    公开(公告)日：2013-09-26

    申请号：US13902498

    申请日：2013-05-24

    Applicant: Micron Technology, Inc.

    Inventor： Fernando Gonzalez ,  Chandra V. Mouli

    IPC: H01L29/66

    CPC classification number: G11C11/401 ,  G11C11/405 ,  G11C11/408 ,  G11C11/409 ,  H01L27/0705 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/66666 ,  H01L29/7841

    Abstract: A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of a substantially physically isolated portion of the bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.

    Abstract translation: 无电容器的存储单元，存储器件，系统和形成无电容器的存储单元的工艺包括在体半导体衬底的基本上物理隔离的部分的有源区中形成存储单元。 在有源区上形成传输晶体管，用于与字线耦合。 无电容器存储单元还包括沿着有效区域的至少一个垂直侧垂直配置的读/写使能晶体管，并且在逻辑状态的读取期间可操作，逻辑状态被存储为电荷的浮动体区域 有效区域，导致传输晶体管的不同可确定的阈值电压。

    Apparatus including a capacitor-less memory cell and related methods
    2.
    发明授权
    Apparatus including a capacitor-less memory cell and related methods 有权
    装置包括无电容器的存储单元及相关方法

    公开(公告)号：US09293185B2

    公开(公告)日：2016-03-22

    申请号：US14246896

    申请日：2014-04-07

    Applicant: Micron Technology, Inc.

    Inventor： Fernando Gonzalez ,  Chandra V. Mouli

    IPC: G11C11/24 ,  G11C11/401 ,  G11C11/405 ,  G11C11/408 ,  H01L27/108 ,  H01L29/78 ,  H01L29/66 ,  G11C11/409 ,  H01L27/07

    CPC classification number: G11C11/401 ,  G11C11/405 ,  G11C11/408 ,  G11C11/409 ,  H01L27/0705 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/66666 ,  H01L29/7841

    Abstract: A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell include forming the capacitor-less memory cell in an active area of a substantially physically isolated portion of a bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.

    Abstract translation: 无电容器的存储单元，存储器件，系统和形成无电容器的存储单元的工艺包括在体半导体衬底的基本上物理隔离的部分的有源区中形成无电容器的存储单元。 在有源区上形成传输晶体管，用于与字线耦合。 无电容器存储单元还包括沿着有效区域的至少一个垂直侧垂直配置的读/写使能晶体管，并且在逻辑状态的读取期间可操作，逻辑状态被存储为电荷的浮动体区域 有效区域，导致传输晶体管的不同可确定的阈值电压。

    Transistor structures and integrated circuitry comprising an array of transistor structures
    3.
    发明授权
    Transistor structures and integrated circuitry comprising an array of transistor structures 有权
    晶体管结构和包括晶体管结构阵列的集成电路

    公开(公告)号：US09129847B2

    公开(公告)日：2015-09-08

    申请号：US14032541

    申请日：2013-09-20

    Applicant: Micron Technology, Inc.

    Inventor： Fernando Gonzalez

    IPC: H01L27/108 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/12

    CPC classification number: H01L27/10802 ,  H01L21/823468 ,  H01L21/84 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841

    Abstract: This invention includes a capacitorless one transistor DRAM cell that includes a pair of spaced source/drain regions received within semiconductive material. An electrically floating body region is disposed between the source/drain regions within the semiconductive material. A first gate spaced is apart from and capacitively coupled to the body region between the source/drain regions. A pair of opposing conductively interconnected second gates are spaced from and received laterally outward of the first gate. The second gates are spaced from and capacitively coupled to the body region laterally outward of the first gate and between the pair of source/drain regions. Methods of forming lines of capacitorless one transistor DRAM cells are disclosed.

    Abstract translation: 本发明包括一个无电容的一晶体管DRAM单元，其包括在半导体材料内接收的一对间隔的源/漏区。 电浮动体区域设置在半导体材料内的源极/漏极区域之间。 间隔开的第一栅极与电源/漏极区域之间的体区分开并电容耦合。 一对相对的导电互连的第二栅极与第一栅极间隔开并横向向外延伸。 第二栅极与第一栅极的横向外侧和一对源极/漏极区之间的体区间隔开并电容耦合。 公开了形成无电容的一个晶体管DRAM单元的线的方法。

    CAPACITOR-LESS MEMORY CELL, DEVICE, SYSTEM AND METHOD OF MAKING SAME
    5.
    发明申请
    CAPACITOR-LESS MEMORY CELL, DEVICE, SYSTEM AND METHOD OF MAKING SAME 审中-公开
    无电容器存储器单元，器件，系统及其制造方法

    公开(公告)号：US20140219017A1

    公开(公告)日：2014-08-07

    申请号：US14246896

    申请日：2014-04-07

    Applicant: Micron Technology, Inc.

    Inventor： Fernando Gonzalez ,  Chandra V. Mouli

    IPC: G11C11/401 ,  H01L29/66

    CPC classification number: G11C11/401 ,  G11C11/405 ,  G11C11/408 ,  G11C11/409 ,  H01L27/0705 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/66666 ,  H01L29/7841

    Abstract: A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell include forming the capacitor-less memory cell in an active area of a substantially physically isolated portion of a bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.

    Abstract translation: 无电容器存储单元，存储器件，系统和形成无电容器的存储单元的工艺包括在体半导体衬底的基本上物理隔离的部分的有源区中形成无电容器存储单元。 在有源区上形成传输晶体管，用于与字线耦合。 无电容器存储单元还包括沿着有效区域的至少一个垂直侧垂直配置的读/写使能晶体管，并且在逻辑状态的读取期间可操作，逻辑状态被存储为电荷的浮动体区域 有效区域，导致传输晶体管的不同可确定的阈值电压。

    Capacitor-less memory cell, device, system and method of making same
    6.
    发明授权
    Capacitor-less memory cell, device, system and method of making same 有权
    无电容存储单元，器件，系统及其制造方法

    公开(公告)号：US08724372B2

    公开(公告)日：2014-05-13

    申请号：US14050500

    申请日：2013-10-10

    Applicant: Micron Technology, Inc.

    Inventor： Fernando Gonzalez ,  Chandra V. Mouli

    IPC: G11C11/24

    CPC classification number: G11C11/401 ,  G11C11/405 ,  G11C11/408 ,  G11C11/409 ,  H01L27/0705 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/66666 ,  H01L29/7841

    Abstract: A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the capacitor-less memory cell in an active area of a substantially physically isolated portion of a bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.

    Abstract translation: 无电容器存储单元，存储器件，系统和形成无电容器的存储单元的工艺包括在体半导体衬底的基本上物理隔离的部分的有源区中形成无电容器存储单元。 在有源区上形成传输晶体管，用于与字线耦合。 无电容器存储单元还包括沿着有效区域的至少一个垂直侧垂直配置的读/写使能晶体管，并且在逻辑状态的读取期间可操作，逻辑状态被存储为电荷的浮动体区域 有效区域，导致传输晶体管的不同可确定的阈值电压。

    CAPACITOR-LESS MEMORY CELL, DEVICE, SYSTEM AND METHOD OF MAKING SAME
    8.
    发明申请
    CAPACITOR-LESS MEMORY CELL, DEVICE, SYSTEM AND METHOD OF MAKING SAME 有权
    无电容器存储器单元，器件，系统及其制造方法

    公开(公告)号：US20140036584A1

    公开(公告)日：2014-02-06

    申请号：US14050500

    申请日：2013-10-10

    Applicant: Micron Technology, Inc.

    Inventor： Fernando Gonzalez ,  Chandra V. Mouli

    IPC: G11C11/409

    CPC classification number: G11C11/401 ,  G11C11/405 ,  G11C11/408 ,  G11C11/409 ,  H01L27/0705 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/66666 ,  H01L29/7841

    Abstract: A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of a substantially physically isolated portion of the bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.

    Abstract translation: 无电容器的存储单元，存储器件，系统和形成无电容器的存储单元的工艺包括在体半导体衬底的基本上物理隔离的部分的有源区中形成存储单元。 在有源区上形成传输晶体管，用于与字线耦合。 无电容器存储单元还包括沿着有效区域的至少一个垂直侧垂直配置的读/写使能晶体管，并且在逻辑状态的读取期间可操作，逻辑状态被存储为电荷的浮动体区域 有效区域，导致传输晶体管的不同可确定的阈值电压。

    MULTI-DIMENSIONAL SOLID STATE LIGHTING DEVICE ARRAY SYSTEM AND ASSOCIATED METHODS AND STRUCTURES
    9.
    发明申请
    MULTI-DIMENSIONAL SOLID STATE LIGHTING DEVICE ARRAY SYSTEM AND ASSOCIATED METHODS AND STRUCTURES 有权
    多维固态照明设备阵列系统及相关方法与结构

    公开(公告)号：US20130292712A1

    公开(公告)日：2013-11-07

    申请号：US13934426

    申请日：2013-07-03

    Applicant: Micron Technology, Inc.

    Inventor： Alan Mondada ,  Fernando Gonzalez ,  Willard L. Hofer

    IPC: H01L33/08

    CPC classification number: H01L33/08 ,  F21V7/04 ,  F21Y2107/40 ,  F21Y2115/10 ,  H01L25/0753 ,  H01L33/507 ,  H01L33/54 ,  H01L33/62 ,  H01L2224/48091 ,  H01L2224/8592 ,  H01L2924/00014

    Abstract: A multi-dimensional solid state lighting (SSL) device array system and method are disclosed. An SSL device includes a support, a pillar having several sloped facets mounted to the support, and a flexible substrate pressed against the pillar. The substrate can carry a plurality of solid state emitters (SSEs) facing in various directions corresponding to the sloped facets of the pillar. The flexible substrate can be a flat substrate prepared using planar mounting techniques, such as wirebonding techniques, before bending the substrate against the pillar.

    Abstract translation: 公开了一种多维固态照明（SSL）设备阵列系统和方法。 SSL装置包括支撑件，具有安装到支撑件上的多个倾斜小平面的支柱以及压靠在支柱上的柔性基板。 基板可以承载面向与柱的倾斜小平面对应的各个方向的多个固态发射器（SSEs）。 柔性基板可以是使用平面安装技术（例如引线接合技术）在将基板弯曲抵靠柱之前制备的平坦基板。

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