公开(公告)号：US10607678B2

公开(公告)日：2020-03-31

申请号：US16269485

申请日：2019-02-06

Applicant: Micron Technology, Inc.

Inventor： Kiyotake Sakurai ,  Yasushi Matsubara

IPC: G11C11/22

Abstract: Methods and apparatuses for erasing data on a plurality of ferroelectric memory cells in a memory cell array in a memory apparatus are disclosed. An example apparatus includes: a memory cell array including a first plurality of word lines; a digit line; and a plurality of ferroelectric memory cells; a control circuit that provides a section select signal and a word line select signal to select a second plurality of word lines among the first plurality of word lines responsive to an address; and an address decoder that activates the second plurality of word lines. Each ferroelectric memory cell includes: a ferroelectric capacitor having a first terminal coupled to a cell plate node and a second terminal coupled to a selection circuit that couples the digit line to the second terminal responsive to a signal on a corresponding word line of the second plurality of word lines.

公开(公告)号：US20200185020A1

公开(公告)日：2020-06-11

申请号：US16793889

申请日：2020-02-18

Applicant: Micron Technology, Inc.

Inventor： Kiyotake Sakurai ,  Yasushi Matsubara

IPC: G11C11/22

Abstract: Methods and apparatuses for erasing data on a plurality of ferroelectric memory cells in a memory cell array in a memory apparatus are disclosed. An example apparatus includes: a memory cell array including a first plurality of word lines; a digit line; and a plurality of ferroelectric memory cells; a control circuit that provides a section select signal and a word line select signal to select a second plurality of word lines among the first plurality of word lines responsive to an address; and an address decoder that activates the second plurality of word lines. Each ferroelectric memory cell includes: a ferroelectric capacitor having a first terminal coupled to a cell plate node and a second terminal coupled to a selection circuit that couples the digit line to the second terminal responsive to a signal on a corresponding word line of the second plurality of word lines.

公开(公告)号：US20190311757A1

公开(公告)日：2019-10-10

申请号：US16387220

申请日：2019-04-17

Applicant: Micron Technology, Inc.

Inventor： Kiyotake Sakurai ,  Yasushi Matsubara

IPC: G11C11/22

Abstract: Methods, systems, and devices for cell bottom node reset in a memory array are described. The memory array may include a plurality of ferroelectric memory cells having a cell bottom node and a cell plate opposite the cell bottom node. A zero voltage may be applied to a plurality of digit lines in the memory array. A plurality of word lines may be activated to electrically coupled the plurality of digit lines to cell bottom node of each of the ferroelectric memory cells. Accordingly, the cell bottom node of each of the ferroelectric memory cells may be reset to the zero voltage.

公开(公告)号：US20190287602A1

公开(公告)日：2019-09-19

申请号：US16269485

申请日：2019-02-06

Applicant: Micron Technology, Inc.

Inventor： Kiyotake Sakurai ,  Yasushi Matsubara

IPC: G11C11/22

Abstract: Methods and apparatuses for erasing data on a plurality of ferroelectric memory cells in a memory cell array in a memory apparatus are disclosed. An example apparatus includes: a memory cell array including a first plurality of word lines; a digit line; and a plurality of ferroelectric memory cells; a control circuit that provides a section select signal and a word line select signal to select a second plurality of word lines among the first plurality of word lines responsive to an address; and an address decoder that activates the second plurality of word lines. Each ferroelectric memory cell includes: a ferroelectric capacitor having a first terminal coupled to a cell plate node and a second terminal coupled to a selection circuit that couples the digit line to the second terminal responsive to a signal on a corresponding word line of the second plurality of word lines.

公开(公告)号：US10229727B1

公开(公告)日：2019-03-12

申请号：US15919994

申请日：2018-03-13

Applicant: Micron Technology, Inc.

Inventor： Kiyotake Sakurai ,  Yasushi Matsubara

IPC: G11C11/22

Abstract: Methods and apparatuses for erasing data on a plurality of ferroelectric memory cells in a memory cell array in a memory apparatus are disclosed. An example apparatus includes: a memory cell array including a first plurality of word lines; a digit line; and a plurality of ferroelectric memory cells; a control circuit that provides a section select signal and a word line select signal to select a second plurality of word lines among the first plurality of word lines responsive to an address; and an address decoder that activates the second plurality of word lines. Each ferroelectric memory cell includes: a ferroelectric capacitor having a first terminal coupled to a cell plate node and a second terminal coupled to a selection circuit that couples the digit line to the second terminal responsive to a signal on a corresponding word line of the second plurality of word lines.