公开(公告)号：US20200335147A1

公开(公告)日：2020-10-22

申请号：US16869510

申请日：2020-05-07

Applicant: Micron Technology, Inc.

Inventor： Kiyotake Sakurai ,  Yasushi Matsubara

IPC: G11C11/22

Abstract: Methods, systems, and devices for cell bottom node reset in a memory array are described. The memory array may include a plurality of ferroelectric memory cells having a cell bottom node and a cell plate opposite the cell bottom node. A zero voltage may be applied to a plurality of digit lines in the memory array. A plurality of word lines may be activated to electrically coupled the plurality of digit lines to cell bottom node of each of the ferroelectric memory cells. Accordingly, the cell bottom node of each of the ferroelectric memory cells may be reset to the zero voltage.

公开(公告)号：US11004492B2

公开(公告)日：2021-05-11

申请号：US16869510

申请日：2020-05-07

Applicant: Micron Technology, Inc.

Inventor： Kiyotake Sakurai ,  Yasushi Matsubara

IPC: G11C11/22 ,  G11C11/56

Abstract: Methods, systems, and devices for cell bottom node reset in a memory array are described. The memory array may include a plurality of ferroelectric memory cells having a cell bottom node and a cell plate opposite the cell bottom node. A zero voltage may be applied to a plurality of digit lines in the memory array. A plurality of word lines may be activated to electrically coupled the plurality of digit lines to cell bottom node of each of the ferroelectric memory cells. Accordingly, the cell bottom node of each of the ferroelectric memory cells may be reset to the zero voltage.

公开(公告)号：US10685694B2

公开(公告)日：2020-06-16

申请号：US16387220

申请日：2019-04-17

Applicant: Micron Technology, Inc.

Inventor： Kiyotake Sakurai ,  Yasushi Matsubara

IPC: G11C11/22 ,  G11C11/56

Abstract: Methods, systems, and devices for cell bottom node reset in a memory array are described. The memory array may include a plurality of ferroelectric memory cells having a cell bottom node and a cell plate opposite the cell bottom node. A zero voltage may be applied to a plurality of digit lines in the memory array. A plurality of word lines may be activated to electrically coupled the plurality of digit lines to cell bottom node of each of the ferroelectric memory cells. Accordingly, the cell bottom node of each of the ferroelectric memory cells may be reset to the zero voltage.

公开(公告)号：US20190051343A1

公开(公告)日：2019-02-14

申请号：US16054785

申请日：2018-08-03

Applicant: Micron Technology, Inc.

Inventor： Kiyotake Sakurai ,  Yasushi Matsubara

IPC: G11C11/22 ,  G11C11/56

Abstract: Methods, systems, and devices for cell bottom node reset in a memory array are described. The memory array may include a plurality of ferroelectric memory cells having a cell bottom node and a cell plate opposite the cell bottom node. A zero voltage may be applied to a plurality of digit lines in the memory array. A plurality of word lines may be activated to electrically coupled the plurality of digit lines to cell bottom node of each of the ferroelectric memory cells. Accordingly, the cell bottom node of each of the ferroelectric memory cells may be reset to the zero voltage.

公开(公告)号：US11742013B2

公开(公告)日：2023-08-29

申请号：US17211556

申请日：2021-03-24

Applicant: Micron Technology, Inc.

Inventor： Kiyotake Sakurai ,  Yasushi Matsubara

IPC: G11C11/22

CPC classification number: G11C11/2275 ,  G11C11/221 ,  G11C11/2257 ,  G11C11/2259

Abstract: Methods and apparatuses for erasing data on a plurality of ferroelectric memory cells in a memory cell array in a memory apparatus are disclosed. An example apparatus includes: a memory cell array including a first plurality of word lines; a digit line; and a plurality of ferroelectric memory cells; a control circuit that provides a section select signal and a word line select signal to select a second plurality of word lines among the first plurality of word lines responsive to an address; and an address decoder that activates the second plurality of word lines. Each ferroelectric memory cell includes: a ferroelectric capacitor having a first terminal coupled to a cell plate node and a second terminal coupled to a selection circuit that couples the digit line to the second terminal responsive to a signal on a corresponding word line of the second plurality of word lines.

公开(公告)号：US10790004B2

公开(公告)日：2020-09-29

申请号：US16218194

申请日：2018-12-12

Applicant: Micron Technology, Inc.

Inventor： Kiyotake Sakurai ,  Takuya Nakanishi ,  Shinji Bessho

IPC: G11C11/406 ,  G11C11/409 ,  G11C11/4091

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for generating a refresh address locally at a memory bank. The memory bank may include or be associated with a bank logic circuit that latches an initial refresh address from a global row address bus for a first pump of a refresh operation. The bank logic circuit then updates the latched refresh address received to generate a new refresh address for a second pump of the refresh operation. A memory device may include multiple memory banks that share the global row address bus.

公开(公告)号：US10311933B2

公开(公告)日：2019-06-04

申请号：US16054785

申请日：2018-08-03

Applicant: Micron Technology, Inc.

Inventor： Kiyotake Sakurai ,  Yasushi Matsubara

IPC: G11C11/22 ,  G11C11/56

Abstract: Methods, systems, and devices for cell bottom node reset in a memory array are described. The memory array may include a plurality of ferroelectric memory cells having a cell bottom node and a cell plate opposite the cell bottom node. A zero voltage may be applied to a plurality of digit lines in the memory array. A plurality of word lines may be activated to electrically coupled the plurality of digit lines to cell bottom node of each of the ferroelectric memory cells. Accordingly, the cell bottom node of each of the ferroelectric memory cells may be reset to the zero voltage.

公开(公告)号：US10056129B1

公开(公告)日：2018-08-21

申请号：US15674382

申请日：2017-08-10

Applicant: Micron Technology, Inc.

Inventor： Kiyotake Sakurai ,  Yasushi Matsubara

IPC: G11C11/22 ,  G11C11/56

CPC classification number: G11C11/2257 ,  G11C11/221 ,  G11C11/2255 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2293 ,  G11C11/2297 ,  G11C11/5657

Abstract: Methods, systems, and devices for cell bottom node reset in a memory array are described. The memory array may include a plurality of ferroelectric memory cells having a cell bottom node and a cell plate opposite the cell bottom node. A zero voltage may be applied to a plurality of digit lines in the memory array. A plurality of word lines may be activated to electrically coupled the plurality of digit lines to cell bottom node of each of the ferroelectric memory cells. Accordingly, the cell bottom node of each of the ferroelectric memory cells may be reset to the zero voltage.

公开(公告)号：US20210210131A1

公开(公告)日：2021-07-08

申请号：US17211556

申请日：2021-03-24

Applicant: Micron Technology, Inc.

Inventor： Kiyotake Sakurai ,  Yasushi Matsubara

IPC: G11C11/22

Abstract: Methods and apparatuses for erasing data on a plurality of ferroelectric memory cells in a memory cell array in a memory apparatus are disclosed. An example apparatus includes: a memory cell array including a first plurality of word lines; a digit line; and a plurality of ferroelectric memory cells; a control circuit that provides a section select signal and a word line select signal to select a second plurality of word lines among the first plurality of word lines responsive to an address; and an address decoder that activates the second plurality of word lines. Each ferroelectric memory cell includes: a ferroelectric capacitor having a first terminal coupled to a cell plate node and a second terminal coupled to a selection circuit that couples the digit line to the second terminal responsive to a signal on a corresponding word line of the second plurality of word lines.

公开(公告)号：US10984848B2

公开(公告)日：2021-04-20

申请号：US16793889

申请日：2020-02-18

Applicant: Micron Technology, Inc.

Inventor： Kiyotake Sakurai ,  Yasushi Matsubara

IPC: G11C11/22

Abstract: Methods and apparatuses for erasing data on a plurality of ferroelectric memory cells in a memory cell array in a memory apparatus are disclosed. An example apparatus includes: a memory cell array including a first plurality of word lines; a digit line; and a plurality of ferroelectric memory cells; a control circuit that provides a section select signal and a word line select signal to select a second plurality of word lines among the first plurality of word lines responsive to an address; and an address decoder that activates the second plurality of word lines. Each ferroelectric memory cell includes: a ferroelectric capacitor having a first terminal coupled to a cell plate node and a second terminal coupled to a selection circuit that couples the digit line to the second terminal responsive to a signal on a corresponding word line of the second plurality of word lines.