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公开(公告)号：US07817386B2
公开(公告)日：2010-10-19
申请号：US11907206
申请日：2007-10-10
IPC分类号： H02H9/00
CPC分类号： H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： An ESD protection circuit suitable for applying in an integrated circuit with separated power domains is provided. The circuit includes a P-type MOSFET coupled between a first circuit in a first power domain and a second circuit in a second power domain. A source terminal of the P-type MOSFET is coupled to a connection node for connecting the first circuit and the second circuit. A gate terminal of the P-type MOSFET is coupled to a positive power line of the second power domain. A drain terminal of the P-type MOSFET is coupled to a negative power line of the second power domain. A body terminal of the P-type MOSFET is also coupled to the connection node.
摘要翻译： 提供一种适用于具有分离电源域的集成电路中的ESD保护电路。 电路包括耦合在第一电源域中的第一电路和第二电源域中的第二电路之间的P型MOSFET。 P型MOSFET的源极端子连接到用于连接第一电路和第二电路的连接节点。 P型MOSFET的栅极端子耦合到第二电源域的正电源线。 P型MOSFET的漏极端子耦合到第二电源域的负电源线。 P型MOSFET的体式端子也耦合到连接节点。
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公开(公告)号：US07755871B2
公开(公告)日：2010-07-13
申请号：US11987222
申请日：2007-11-28
IPC分类号： H02H9/04
CPC分类号： H02H9/046
摘要： An ESD protection circuit including a clamping module and a detecting module is provided. The clamping module is coupled between a positive power line and a negative power line. The detecting module includes a triggering unit, a resistor, and a MOS capacitor. An output terminal of the triggering unit is used for triggering the clamping module. The resistor is coupled between the positive power line and an input terminal of the triggering unit. The MOS capacitor has a first end and a second end. The first end is coupled to the input terminal of the triggering unit. During a normal power operation, a switching terminal of the triggering unit enables the second end of the MOS capacitor to be coupled with the positive power line. Thereby, the gate tunneling leakage is eliminated and the problem of mistriggering is prevented.
摘要翻译： 提供了包括夹紧模块和检测模块的ESD保护电路。 夹紧模块耦合在正电源线和负电源线之间。 检测模块包括触发单元，电阻器和MOS电容器。 触发单元的输出端子用于触发夹紧模块。 电阻器耦合在正电源线和触发单元的输入端之间。 MOS电容器具有第一端和第二端。 第一端耦合到触发单元的输入端。 在正常电力操作期间，触发单元的开关端子使MOS电容器的第二端与正电源线耦合。 由此，消除了栅极隧道泄漏，并且防止了错误捕捉的问题。
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公开(公告)号：US20090032838A1
公开(公告)日：2009-02-05
申请号：US12113912
申请日：2008-05-01
IPC分类号： H01L29/747
CPC分类号： H01L27/0262 , H01L29/747 , H01L29/87
摘要： The present invention discloses a symmetric bidirectional silicon-controlled rectifier, which comprises: a substrate; a buried layer formed on the substrate; a first well, a middle region and a second well, which are sequentially formed on the buried layer side-by-side; a first semiconductor area and a second semiconductor area both formed inside the first well; a third semiconductor area formed in a junction between the first well and the middle region, wherein a first gate is formed over a region between the second and third semiconductor areas; a fourth semiconductor area and a fifth semiconductor area both formed inside the second well; a sixth semiconductor area formed in a junction between the second well and the middle region, wherein a second gate is formed over a region between the fifth and sixth semiconductor areas.
摘要翻译： 本发明公开了一种对称双向硅控整流器，其包括：衬底; 形成在基板上的掩埋层; 第一阱，中间区域和第二阱，并排地依次形成在掩埋层上; 第一半导体区域和第二半导体区域都形成在第一阱内; 形成在所述第一阱和所述中间区域之间的接合处的第三半导体区域，其中在所述第二和第三半导体区域之间的区域上形成第一栅极; 形成在第二阱内的第四半导体区域和第五半导体区域; 形成在所述第二阱和所述中间区域之间的接合处的第六半导体区域，其中在所述第五和第六半导体区域之间的区域上形成第二栅极。
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公开(公告)号：US20080151446A1
公开(公告)日：2008-06-26
申请号：US11613193
申请日：2006-12-20
IPC分类号： H02H9/00
CPC分类号： H01L27/027 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) protection device and a layout thereof are provided. A bias conducting wire is mainly used to couple each base of a plurality of parasitic transistors inside ESD elements together, in order to simultaneously trigger all the parasitic transistors to bypass the ESD current, avoid the elements of a core circuit being damaged, and solve the non-uniform problem of bypassing the ESD current when ESD occurs. Furthermore, in the ESD protection layout, it only needs to add another doped region on a substrate neighboring to, but not contacting, doped regions of the ESD protection elements and use contacts to connect the added doped region, so as to couple each base of the parasitic transistors together without requiring for additional layout area.
摘要翻译： 提供静电放电（ESD）保护装置及其布局。 偏置导线主要用于将ESD元件内的多个寄生晶体管的每个基极耦合在一起，以便同时触发所有寄生晶体管绕过ESD电流，避免核心电路的元件被损坏，并解决 当ESD发生时绕过ESD电流的非均匀问题。 此外，在ESD保护布局中，仅需要在与ESD保护元件的掺杂区域相邻但不接触的衬底上添加另一个掺杂区域，并使用触点来连接所添加的掺杂区域，以便将 寄生晶体管一起而不需要额外的布局区域。
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公开(公告)号：US08773826B2
公开(公告)日：2014-07-08
申请号：US13598194
申请日：2012-08-29
IPC分类号： H02H9/00
CPC分类号： H02H9/046 , H01L2924/0002 , H01L2924/00
摘要： A power-rail ESD clamp circuit with a silicon controlled rectifier and a control module is provided. The silicon controlled rectifier is connected to a high voltage level and a low voltage level for bearing a current flow. The control module is connected to the silicon controlled rectifier in parallel, and includes a PMOS, a NMOS, at least one output diode, a resistor and a conducting string. The silicon controlled rectifier is a P+ or N+ triggered silicon controlled rectifier. By employing the novel power-rail ESD clamp circuit, it is extraordinarily advantageous of reducing both a standby leakage current and layout area while implementation.
摘要翻译： 提供了具有可控硅整流器和控制模块的电力轨道ESD钳位电路。 可控硅整流器连接到高电压电平和低电压电平以承受电流。 控制模块并联连接到可控硅整流器，并且包括PMOS，NMOS，至少一个输出二极管，电阻器和导电串。 可控硅整流器是P +或N +触发的可控硅整流器。 通过采用新型的电源轨ESD钳位电路，在实现时减少备用漏电流和布局面积是非常有利的。
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公开(公告)号：US20140063663A1
公开(公告)日：2014-03-06
申请号：US13598194
申请日：2012-08-29
IPC分类号： H02H9/04
CPC分类号： H02H9/046 , H01L2924/0002 , H01L2924/00
摘要： A power-rail ESD clamp circuit with a silicon controlled rectifier and a control module is provided. The silicon controlled rectifier is connected to a high voltage level and a low voltage level for bearing a current flow. The control module is connected to the silicon controlled rectifier in parallel, and includes a PMOS, a NMOS, at least one output diode, a resistor and a conducting string. The silicon controlled rectifier is a P+ or N+ triggered silicon controlled rectifier. By employing the novel power-rail ESD clamp circuit, it is extraordinarily advantageous of reducing both a standby leakage current and layout area while implementation.
摘要翻译： 提供了具有可控硅整流器和控制模块的电力轨道ESD钳位电路。 可控硅整流器连接到高电压电平和低电压电平以承受电流。 控制模块并联连接到可控硅整流器，并且包括PMOS，NMOS，至少一个输出二极管，电阻器和导电串。 可控硅整流器是P +或N +触发的可控硅整流器。 通过采用新型的电源轨ESD钳位电路，在实现时减少备用漏电流和布局面积是非常有利的。
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公开(公告)号：US08049247B2
公开(公告)日：2011-11-01
申请号：US12113410
申请日：2008-05-01
IPC分类号： H01L29/747
CPC分类号： H01L29/747 , H01L27/0262 , H01L29/87
摘要： The present invention discloses an asymmetric bidirectional silicon-controlled rectifier, which comprises: a second conduction type substrate; a first conduction type undoped epitaxial layer formed on the substrate; a first well and a second well both formed inside the undoped epitaxial layer and separated by a portion of the undoped epitaxial layer; a first buried layer formed in a junction between the first well and the substrate; a second buried layer formed in a junction between the second well and the substrate; a first and a second semiconductor area with opposite conduction type both formed inside the first well; a third and a fourth semiconductor area with opposite conduction type both formed inside the second well, wherein the first and second semiconductor areas are connected to the anode of the silicon-controlled rectifier, and the third and fourth semiconductor areas are connected to the cathode of the silicon-controlled rectifier.
摘要翻译： 本发明公开了一种不对称双向硅控整流器，其包括：第二导电型衬底; 形成在基板上的第一导电型未掺杂外延层; 第一阱和第二阱都形成在未掺杂的外延层内部并由未掺杂的外延层的一部分分离; 第一掩埋层，形成在所述第一阱和所述衬底之间的接合处; 第二掩埋层，形成在所述第二阱和所述衬底之间的接合处; 在第一阱内形成具有相反导电类型的第一和第二半导体区域; 具有相反导电类型的第三和第四半导体区域都形成在第二阱内部，其中第一和第二半导体区域连接到可控硅整流器的阳极，并且第三和第四半导体区域连接到 硅控整流器。
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公开(公告)号：US07705404B2
公开(公告)日：2010-04-27
申请号：US11613193
申请日：2006-12-20
IPC分类号： H01L23/62
CPC分类号： H01L27/027 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) protection device and a layout thereof are provided. A bias conducting wire is mainly used to couple each base of a plurality of parasitic transistors inside ESD elements together, in order to simultaneously trigger all the parasitic transistors to bypass the ESD current, avoid the elements of a core circuit being damaged, and solve the non-uniform problem of bypassing the ESD current when ESD occurs. Furthermore, in the ESD protection layout, it only needs to add another doped region on a substrate neighboring to, but not contacting, doped regions of the ESD protection elements and use contacts to connect the added doped region, so as to couple each base of the parasitic transistors together without requiring for additional layout area.
摘要翻译： 提供静电放电（ESD）保护装置及其布局。 偏置导线主要用于将ESD元件内的多个寄生晶体管的每个基极耦合在一起，以便同时触发所有寄生晶体管绕过ESD电流，避免核心电路的元件被损坏，并解决 当ESD发生时绕过ESD电流的非均匀问题。 此外，在ESD保护布局中，仅需要在与ESD保护元件的掺杂区域相邻但不接触的衬底上添加另一个掺杂区域，并使用触点来连接所添加的掺杂区域，以便将 寄生晶体管一起而不需要额外的布局区域。
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公开(公告)号：US07889470B2
公开(公告)日：2011-02-15
申请号：US12656495
申请日：2010-02-01
IPC分类号： H02H9/00
CPC分类号： H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： An ESD protection circuit is provided. The circuit includes a discharging component, a diode, and an ESD detection circuit. The discharging component is coupled between an input/output pad and a first power line of an IC. The diode is coupled between the input/output pad and a second power line of the IC in a forward direction toward the second power line. The ESD detection circuit includes a capacitor, a resistor, and a triggering component. The capacitor and the resistor are formed in series and coupled between the first power line and the second power line. The triggering component has a positive power end coupled to the input/output pad and a negative power end coupled to the first power line. An input of the triggering component is coupled to a node between the capacitor and the resistor.
摘要翻译： 提供ESD保护电路。 电路包括放电元件，二极管和ESD检测电路。 放电元件耦合在IC的输入/输出焊盘和第一电源线之间。 所述二极管在所述输入/输出焊盘和所述IC的第二电源线之间朝向所述第二电力线向前方连接。 ESD检测电路包括电容器，电阻器和触发部件。 电容器和电阻器串联形成并耦合在第一电源线和第二电源线之间。 触发组件具有耦合到输入/输出焊盘的正功率端和耦合到第一电源线的负功率端。 触发元件的输入耦合到电容器和电阻器之间的节点。
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公开(公告)号：US07786504B2
公开(公告)日：2010-08-31
申请号：US12076556
申请日：2008-03-20
申请人： Wen-Yi Chen , Ryan Hsin-Chin Jiang , Ming-Dou Ker
发明人： Wen-Yi Chen , Ryan Hsin-Chin Jiang , Ming-Dou Ker
IPC分类号： H01L29/74
CPC分类号： H01L27/0262 , H01L29/747 , H01L29/87
摘要： The present invention discloses a bidirectional PNPN silicon-controlled rectifier comprising: a p-type substrate; a N-type epitaxial layer; a P-type well and two N-type wells all formed inside the N-type epitaxial layer with the two N-type wells respectively arranged at two sides of the P-type well; a first semiconductor area, a second semiconductor area and a third semiconductor area all formed inside the P-type well and all coupled to an anode, wherein the second semiconductor area and the third semiconductor area are respectively arranged at two sides of the first semiconductor area, and wherein the first semiconductor area is of first conduction type, and the second semiconductor area and the third semiconductor area are of second conduction type; and two P-type doped areas respectively formed inside the N-type wells, wherein each P-type doped area has a fourth semiconductor area neighboring the P-type well and a fifth semiconductor area, and wherein both the fourth semiconductor area and the fifth semiconductor area are coupled to a cathode, and wherein the fourth semiconductor area is of second conduction type, and the fifth semiconductor area is of first conduction type.
摘要翻译： 本发明公开了一种双向PNPN可控硅整流器，包括：p型衬底; N型外延层; 所有形成在N型外延层内的P型阱和两个N型阱，两个N型阱分别布置在P型阱的两侧; 所述第一半导体区域，第二半导体区域和第三半导体区域全部形成在所述P型阱内并全部耦合到阳极，其中所述第二半导体区域和所述第三半导体区域分别布置在所述第一半导体区域的第二半导体区域 并且其中所述第一半导体区域是第一导电类型，并且所述第二半导体区域和所述第三半导体区域是第二导电类型; 分别形成在N型阱内部的两个P型掺杂区域，其中每个P型掺杂区域具有与P型阱相邻的第四半导体区域和第五半导体区域，并且其中第四半导体区域和第五半导体区域 半导体区域耦合到阴极，并且其中第四半导体区域是第二导电类型，并且第五半导体区域是第一导电类型。
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