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公开(公告)号：US20240355810A1
公开(公告)日：2024-10-24
申请号：US18762703
申请日：2024-07-03
Inventor： TZU-HENG CHANG , HSIN-YU CHEN , PIN-HSIN CHANG
CPC classification number: H01L27/0266 , H02H9/046
Abstract: The present disclosure provides electrostatic discharge circuits and structures and methods for operating the electrostatic discharge circuits and structures. A circuit includes a first transistor and a second transistor. Each of the first transistor and second transistor includes a drain, a source, and a gate. The drain of the first transistor is connected to a first terminal; the source thereof is connected to receive a first voltage, and the gate thereof is connected to receive a second voltage different from the first voltage. The source and the gate of the second transistor are connected to receive the second voltage, and the drain thereof is connected to the first terminal. In response to the terminal reaching a trigger voltage, the first transistor is configured to be turned on, such that electrostatic charges at the first terminal are configured to be discharged through the first transistor.
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公开(公告)号：US20240329708A1
公开(公告)日：2024-10-03
申请号：US18697441
申请日：2022-06-28
Inventor： Sanxia CHEN , Tiejun LIU , Jing JI
CPC classification number: G06F1/28 , G06F1/266 , G06F13/4068 , H01L27/0266 , G06F2213/0026
Abstract: A method, circuit and apparatus for protecting power supply of a peripheral component interconnect express (PCIE) card, and a medium are provided, card hardware design. When the PCIE card is not completely inserted into a slot of a server, a first power supply and a second power supply are controlled to release electric energy, a controller is controlled; to turn off a first MOS transistor, and a load is charged with the electric energy released by the second power supply. When the PCIE card is completely inserted into the slot of the server, a PRSNT #signal is generated, a second MOS transistor is controlled to be turned on, and the controller is controlled to turn on the first MOS transistor. When the PCIE card is not completely pulled out, the second MOS transistor is controlled to be turned off, and the controller is controlled to turn off the first MOS transistor.
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公开(公告)号：US12101027B2
公开(公告)日：2024-09-24
申请号：US17750932
申请日：2022-05-23
Applicant: Nordic Semiconductor ASA
Inventor： Daniel Pasti Mioni , Jarmo Väänänen
IPC: H02M3/156 , H01L27/02 , H02M3/158 , H03K17/687
CPC classification number: H02M3/1566 , H01L27/0266 , H02M3/158 , H03K17/6871
Abstract: According to an aspect, there is provided an apparatus comprising: a bulk-controlled switch circuit comprising a first transistor coupled to a load and having a source coupled to a source voltage and a drain coupled to a drain voltage, a second transistor and a third transistor coupled, in parallel with the first transistor, to one another in series between the source voltage and the drain voltage, wherein a bulk of the first transistor is coupled with bulks of the second transistor and the third transistor, wherein a gate of the second transistor is coupled to the source voltage via a first impedance circuit and a gate of the third transistor is coupled to the drain voltage via a second impedance circuit to form a comparator switch controlled by the source voltage and the drain voltage and to dynamically switch a greater one of the source voltage and the drain voltage to the load; a first current generator circuit and a second current generator circuit; a first current mirror circuit biased by the first current generator circuit, responsive to the source voltage, and configured to trigger the second transistor to couple the source voltage to the load when the source voltage is above the drain voltage; a second current mirror circuit biased by the second current generator circuit, responsive to the drain voltage, and configured to trigger the third transistor to couple the drain voltage to the load when the drain voltage is above the source voltage.
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公开(公告)号：US12094870B2
公开(公告)日：2024-09-17
申请号：US18356217
申请日：2023-07-21
Inventor： Tzu-Heng Chang , Hsin-Yu Chen , Pin-Hsin Chang
CPC classification number: H01L27/0266 , H02H9/046
Abstract: The present disclosure provides electrostatic discharge circuits and structures and methods for operating the electrostatic discharge circuits and structures. A circuit includes a first transistor and a second transistor. The first transistor includes a drain, a source, a gate, and a bulk. The drain of the first transistor is connected to a first terminal. The source of the first transistor is connected to receive a first voltage. The gate and the bulk of the first transistor is connected to receive a second voltage. The second transistor includes a drain, a source, a gate, and a bulk. The source, the gate, and the bulk of the second transistor is connected to receive the second voltage. The drain of the second transistor is connected to the first terminal. In response to the terminal reaching a trigger voltage, the first transistor is configured to be turned on.
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公开(公告)号：US20240170952A1
公开(公告)日：2024-05-23
申请号：US17790462
申请日：2022-03-23
Applicant: ChangXin Memory Technologies, Inc.
Inventor： Yingtao Zhang , Pan Mao , Junjie Liu , Lingxin Zhu , Bin Song , Qian Xu , Tieh-Chiang Wu
CPC classification number: H02H9/02 , H01L27/0255 , H01L27/0262 , H01L27/0266 , H01L27/0292
Abstract: Embodiments of the present disclosure relate to an electrostatic protection structure and an electrostatic protection circuit. The electrostatic protection structure includes: a SCR structure and a trigger structure; the SCR structure includes: a well region of a second conductivity type and a first well of a first conductivity type region, a first-doped region of the first conductivity type, and a first-doped region of the second conductivity type; the trigger structure includes: a first-doped region of the second conductivity type, a second well region of the first conductivity type, a second-doped region of two conductivity types, a third-doped region of the second conductivity type, a fourth-doped region of the second conductivity type, and a first gate electrode. The electrostatic protection structure weakens the positive feedback of the parasitic transistor in the SCR device, improves the anti-latch capability of the device, realizes stronger protection capability, and enhances the reliability of the circuit.
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Patent Agency Ranking
公开(公告)号：US11990462B2
公开(公告)日：2024-05-21
申请号：US18384883
申请日：2023-10-29
Applicant: Monolithic 3D Inc.
Inventor： Zvi Or-Bach , Brian Cronquist
IPC: H01L25/18 , H01L21/28 , H01L21/324 , H01L23/48 , H01L25/065 , H01L27/02 , H01L27/088 , H01L29/66 , H01L29/78
CPC classification number: H01L25/18 , H01L21/28194 , H01L21/324 , H01L23/481 , H01L25/0657 , H01L27/0266 , H01L27/0886 , H01L29/66795 , H01L29/785 , H01L2225/06541
Abstract: A semiconductor device including: a first silicon layer including a first single crystal silicon layer; first transistors with a single crystal channel and overlaid by a first metal layer; overlaid by a second metal layer; overlaid by a third metal layer; a second level with second transistors and including a metal gate, and then disposed over the third metal layer; the second level is overlaid by a third level with third transistors; and then overlaid by a fourth metal layer; fourth overlaid by a fifth metal layer; parts of the second transistors are made with Atomic Layer Deposition (“ALD”); the fifth metal layer average thickness is greater than the third metal layer average thickness by at least 50%; at least one element within at least one of the second transistors has been processed independently of the third transistors.
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公开(公告)号：US11990192B2
公开(公告)日：2024-05-21
申请号：US17684190
申请日：2022-03-01
Inventor： Toshiaki Dozaka
CPC classification number: G11C17/18 , H01L27/0266 , H01L27/0288 , H01L27/0292 , H02H9/045 , G11C17/16
Abstract: According to one embodiment, an integrated circuit includes a first power supply line, a protection circuit, an internal circuit, a second transistor, and a shutoff control circuit. A first power supply voltage is supplied to the first power supply line. The protection circuit is connected to the first power supply line. The internal circuit includes a first transistor whose breakdown voltage is lower than the first power supply voltage. A drain or a source of the first transistor is connected to the first power supply line. The second transistor is on the first power supply line between the protection circuit and the internal circuit and is configured to switch between conduction and non-conduction states to connect and disconnect the protection circuit and the internal circuit from one another along the first power supply line. The shutoff control circuit is configured to turn off the second transistor during an ESD operation.
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公开(公告)号：US11984515B2
公开(公告)日：2024-05-14
申请号：US17394080
申请日：2021-08-04
Applicant: NEXPERIA B.V.
Inventor： Hans-Martin Ritter , Steffen Holland , Guido Notermans , Joachim Utzig , Vasantha Kumar Vaddagere Nagaraju
CPC classification number: H01L29/87 , H01L27/0255 , H01L29/0684 , H01L27/0259 , H01L27/0266 , H01L27/0288
Abstract: A semiconductor device is provided that includes a first n+ region, a first p+ region within the first n+ region, a second n+ region, a second p+ region, positioned between the first n+ region and the second n+ region. The first n+ region, the second n+ region and the second p+ region are positioned within a p− region. A first space charge region and a second space charge region are formed within the p− region. The first space region is positioned between the first n+ region and the second p+ region, and the second space region is positioned between the second p+ region and the second n+ region.
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公开(公告)号：US11979044B2
公开(公告)日：2024-05-07
申请号：US17376507
申请日：2021-07-15
Applicant: Snap Inc.
IPC: H02J7/00 , G02C5/14 , G02C11/00 , H01L27/02 , H01R13/62 , H02J7/04 , H02J7/34 , H03K19/0185 , H04B3/56 , H04B3/54
CPC classification number: H02J7/0034 , G02C5/146 , G02C11/10 , H01L27/0266 , H01R13/6205 , H02J7/0045 , H02J7/0068 , H02J7/04 , H02J7/345 , H03K19/018557 , H04B3/56 , G02C11/00 , H02J7/00 , H02J7/00034 , H02J7/00302 , H02J7/00306 , H04B3/548 , H04B2203/5454 , H04B2203/547
Abstract: Methods and devices for wired charging and communication with a wearable device are described. In one embodiment, a symmetrical contact interface comprises a first contact pad and a second contact pad, and particular wired circuitry is coupled to the first and second contact pad to enable charging as well as receive and transmit communications via the contact pads as part of various device states.
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公开(公告)号：US11961835B2
公开(公告)日：2024-04-16
申请号：US17520697
申请日：2021-11-07
Applicant: International Business Machines Corporation
Inventor： Effendi Leobandung
IPC: H01L27/02 , H01L29/417
CPC classification number: H01L27/0266 , H01L29/41766
Abstract: A circuit for monitoring usage of an active field effect transistor (FET) includes the active FET and a reference FET, formed in a same structure as the active FET. The active FET and the reference FET both are pFET or both are nFET, and are stacked on each other at a common gate. The circuit also includes a differential current sense circuit (DCSC) and a plurality of switches for connecting terminals of the FETs to logic voltage, ground voltage, and/or the DCSC. The DCSC is configured to measure and compare currents through each of the active and reference FETs when a threshold voltage is applied to the common gate.
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