公开(公告)号：US20060038590A1

公开(公告)日：2006-02-23

申请号：US11251399

申请日：2005-10-14

申请人： James Lundberg ,  Raymond Bertram

发明人： James Lundberg ,  Raymond Bertram

IPC分类号： H03K19/096

CPC分类号： H03K19/0963

摘要： A P-domino latch includes a domino stage, a write stage, an inverter, a low keeper path, a high keeper path, and an output stage. The domino stage is coupled to an approximately symmetric clock signal, and evaluates a logic function according to the states of at least one data signal and the approximately symmetric clock signal, where the domino stage pre-charges a pre-charged node low when the approximately symmetric clock signal is high, and discharges the pre-charged node to a high state if the logic function evaluates when the approximately symmetric clock signal is low, and keeps the pre-charged node low if the logic function fails to evaluate when the approximately symmetric clock signal is low, where a latching state of the at least one data signal is provided to the domino stage when the approximately symmetric clock signal is low.

摘要翻译： P多米诺骨牌包括多米诺骨牌阶段，写阶段，逆变器，低守门员路径，高守门员路径和输出阶段。 多米诺骨牌阶段耦合到近似对称的时钟信号，并且根据至少一个数据信号和近似对称的时钟信号的状态来评估逻辑功能，其中多米诺舞台预充电节点在大约 对称时钟信号为高电平，并且如果逻辑功能在近似对称时钟信号为低电平时估计预充电节点，则将预充电节点放电，并且如果逻辑功能不能评估何时近似对称 时钟信号为低，其中当近似对称的时钟信号为低时，至少一个数据信号的锁存状态被提供给多米诺骨牌阶段。

公开(公告)号：US20050216630A1

公开(公告)日：2005-09-29

申请号：US10946828

申请日：2004-09-22

申请人： Darius Gaskins ,  James Lundberg

发明人： Darius Gaskins ,  James Lundberg

IPC分类号： G06F13/00 ,  G06F13/40

CPC分类号： G06F13/4072

摘要： A sense mechanism for data bus inversion including a first memory device and an analog adder. The first memory device stores bits of the bus in a previous bus cycle. The analog adder compares the bits of the bus in the previous bus cycle with bits of the bus in a current bus cycle and provides a data inversion signal indicative of whether more than half of the bits of the bus have changed state. The analog adder operates as a bus state change sense device which rapidly evaluates bus state changes from one bus cycle to the next. The data inversion signal is used for selectively inverting the data bits of the bus and indicating bus inversion according to data bus inversion operation, such as according to X86 microprocessor protocol.

摘要翻译： 一种用于数据总线反转的检测机制，包括第一存储器件和模拟加法器。 第一个存储器件在先前的总线周期中存储总线的位。 模拟加法器将当前总线周期中的总线的总线位与当前总线周期中的总线的比特进行比较，并提供一个数据反转信号，指示总线的一半以上是否有改变状态。 模拟加法器作为总线状态改变检测装置进行操作，其将总线状态变化从一个总线周期快速评估到下一个总线周期。 数据反转信号用于根据数据总线反转操作，例如根据X86微处理器协议选择性地反相总线的数据位和指示总线反转。

公开(公告)号：US20050195543A1

公开(公告)日：2005-09-08

申请号：US10833401

申请日：2004-04-28

申请人： James Lundberg

发明人： James Lundberg

IPC分类号： H03K17/60 ,  H03K19/0175

CPC分类号： H03K19/00315

摘要： An overvoltage protection circuit for a receiver including first and second pass devices and a protection control circuit. The receiver detects the state of a high voltage level input signal using a switching threshold based on a low voltage level source voltage. The receiver has a maximum voltage limit between the low and high voltage levels. The first pass device passes the input signal up to a first voltage level below the source voltage. The second pass device is effectively coupled in parallel with the first pass device. The protection control circuit controls the second pass device to allow the input signal to rise above the first voltage level up to a threshold voltage that is above the source voltage sufficient to meet the logic switching threshold yet below the maximum voltage limit.

摘要翻译： 一种用于包括第一和第二通过装置和保护控制电路的接收器的过电压保护电路。 接收机使用基于低电压电平源电压的开关阈值来检测高电压电平输入信号的状态。 接收器在低电平和高电平之间具有最大电压限制。 第一通过器件将输入信号传递到低于源极电压的第一电压电平。 第二通道装置与第一通道装置并联有效耦合。 保护控制电路控制第二通过器件以允许输入信号升高到高于第一电压电平，直到高于源极电压的阈值电压足以满足逻辑开关阈值但低于最大电压限制。

公开(公告)号：US20050055538A1

公开(公告)日：2005-03-10

申请号：US10730168

申请日：2003-12-06

申请人： James Lundberg

发明人： James Lundberg

IPC分类号： G06F15/00 ,  H03K19/096

CPC分类号： H03K19/0963

摘要： A dynamic logic return-to-zero (RTZ) latching mechanism including a complementary pair of evaluation devices responsive to a clock signal, a dynamic evaluator, delayed inversion logic, and latching logic. The dynamic evaluator is coupled between the complementary pair of evaluation devices at a pre-charged node and evaluates a logic function based on at least one input data signal. The latching logic asserts the logic state of an output node based on the state of the pre-charged node during an evaluation period between an operative edge of the clock signal and the next edge of an evaluation complete signal, which is a delayed and inverted version of the clock signal. The output node is returned to zero between evaluation periods. A footless latching domino circuit may be added to convert the RTZ output to a registered output signal.

摘要翻译： 动态逻辑归零（RTZ）锁存机制包括响应于时钟信号的一对互补的评估装置，动态评估器，延迟反转逻辑和锁存逻辑。 动态评估器在预充电节点处耦合在互补的评估装置对之间，并基于至少一个输入数据信号来评估逻辑功能。 锁定逻辑在时钟信号的操作边缘与评估完成信号的下一个边缘之间的评估周期期间基于预充电节点的状态来断言输出节点的逻辑状态，该评估完成信号是延迟和反向版本 的时钟信号。 输出节点在评估周期之间返回到零。 可以添加一个无脚锁定多米诺骨牌电路，以将RTZ输出转换为已注册的输出信号。