公开(公告)号：US07271679B2

公开(公告)日：2007-09-18

申请号：US11172375

申请日：2005-06-30

申请人： James Lundberg ,  Robert A. Zigler ,  For Sander Lam

发明人： James Lundberg ,  Robert A. Zigler ,  For Sander Lam

IPC分类号： H01P5/00 ,  H01Q1/42

CPC分类号： H01Q1/002 ,  H01Q1/22

摘要： A system useful in providing communications with automatic data collection (ADC) devices employs an antenna located in a potentially hazardous environment, a radio circuit located in a non-hazardous environment, and a coupling apparatus to provide an interface between the antenna and the radio circuit that prevents electrical discharges from occurring in the potentially hazardous environment.

摘要翻译： 用于提供与自动数据采集（ADC）设备通信的系统采用位于潜在危险环境中的天线，位于非危险环境中的无线电电路，以及提供天线与无线电路之间的接口的耦合装置 这可以防止在潜在危险环境中发生放电。

公开(公告)号：US20060119443A1

公开(公告)日：2006-06-08

申请号：US11297622

申请日：2005-12-08

申请人： Mir Azam ,  James Lundberg

发明人： Mir Azam ,  James Lundberg

IPC分类号： H03L7/00

CPC分类号： H03L7/093 ,  H03L7/099 ,  H03L7/107 ,  H03L7/18 ,  H03L2207/04 ,  H03L2207/05

摘要： A damping coefficient variation mechanism for a PLL including a bias controller, a gain control circuit, and an oscillator circuit. The PLL receives an input clock signal and provides an output clock at a frequency that is the frequency of the input clock multiplied by a clock multiplier. The bias controller has an input receiving a loop control signal and an output providing one or more bias signals. The gain control circuit has bias inputs receiving the bias signals, a gain control input receiving a gain control value, and an output providing a control signal. The oscillator circuit has an input receiving the control signal and an output providing the output clock signal. The gain control circuit provides the control signal to adjust frequency of the output clock signal based on the loop control signal at a gain determined by the gain control value.

摘要翻译： 一种用于PLL的阻尼系数变化机构，包括偏置控制器，增益控制电路和振荡器电路。 PLL接收输入时钟信号，并以输入时钟频率乘以时钟倍频的频率提供输出时钟。 偏置控制器具有接收回路控制信号的输入端和提供一个或多个偏置信号的输出。 增益控制电路具有接收偏置信号的偏置输入，接收增益控制值的增益控制输入和提供控制信号的输出。 振荡器电路具有接收控制信号的输入端和提供输出时钟信号的输出。 增益控制电路提供控制信号，以由增益控制值确定的增益基于环路控制信号来调节输出时钟信号的频率。

公开(公告)号：US20060038590A1

公开(公告)日：2006-02-23

申请号：US11251399

申请日：2005-10-14

申请人： James Lundberg ,  Raymond Bertram

发明人： James Lundberg ,  Raymond Bertram

IPC分类号： H03K19/096

CPC分类号： H03K19/0963

摘要： A P-domino latch includes a domino stage, a write stage, an inverter, a low keeper path, a high keeper path, and an output stage. The domino stage is coupled to an approximately symmetric clock signal, and evaluates a logic function according to the states of at least one data signal and the approximately symmetric clock signal, where the domino stage pre-charges a pre-charged node low when the approximately symmetric clock signal is high, and discharges the pre-charged node to a high state if the logic function evaluates when the approximately symmetric clock signal is low, and keeps the pre-charged node low if the logic function fails to evaluate when the approximately symmetric clock signal is low, where a latching state of the at least one data signal is provided to the domino stage when the approximately symmetric clock signal is low.

摘要翻译： P多米诺骨牌包括多米诺骨牌阶段，写阶段，逆变器，低守门员路径，高守门员路径和输出阶段。 多米诺骨牌阶段耦合到近似对称的时钟信号，并且根据至少一个数据信号和近似对称的时钟信号的状态来评估逻辑功能，其中多米诺舞台预充电节点在大约 对称时钟信号为高电平，并且如果逻辑功能在近似对称时钟信号为低电平时估计预充电节点，则将预充电节点放电，并且如果逻辑功能不能评估何时近似对称 时钟信号为低，其中当近似对称的时钟信号为低时，至少一个数据信号的锁存状态被提供给多米诺骨牌阶段。

公开(公告)号：US20050216630A1

公开(公告)日：2005-09-29

申请号：US10946828

申请日：2004-09-22

申请人： Darius Gaskins ,  James Lundberg

发明人： Darius Gaskins ,  James Lundberg

IPC分类号： G06F13/00 ,  G06F13/40

CPC分类号： G06F13/4072

摘要： A sense mechanism for data bus inversion including a first memory device and an analog adder. The first memory device stores bits of the bus in a previous bus cycle. The analog adder compares the bits of the bus in the previous bus cycle with bits of the bus in a current bus cycle and provides a data inversion signal indicative of whether more than half of the bits of the bus have changed state. The analog adder operates as a bus state change sense device which rapidly evaluates bus state changes from one bus cycle to the next. The data inversion signal is used for selectively inverting the data bits of the bus and indicating bus inversion according to data bus inversion operation, such as according to X86 microprocessor protocol.

摘要翻译： 一种用于数据总线反转的检测机制，包括第一存储器件和模拟加法器。 第一个存储器件在先前的总线周期中存储总线的位。 模拟加法器将当前总线周期中的总线的总线位与当前总线周期中的总线的比特进行比较，并提供一个数据反转信号，指示总线的一半以上是否有改变状态。 模拟加法器作为总线状态改变检测装置进行操作，其将总线状态变化从一个总线周期快速评估到下一个总线周期。 数据反转信号用于根据数据总线反转操作，例如根据X86微处理器协议选择性地反相总线的数据位和指示总线反转。

公开(公告)号：US20050195543A1

公开(公告)日：2005-09-08

申请号：US10833401

申请日：2004-04-28

申请人： James Lundberg

发明人： James Lundberg

IPC分类号： H03K17/60 ,  H03K19/0175

CPC分类号： H03K19/00315

摘要： An overvoltage protection circuit for a receiver including first and second pass devices and a protection control circuit. The receiver detects the state of a high voltage level input signal using a switching threshold based on a low voltage level source voltage. The receiver has a maximum voltage limit between the low and high voltage levels. The first pass device passes the input signal up to a first voltage level below the source voltage. The second pass device is effectively coupled in parallel with the first pass device. The protection control circuit controls the second pass device to allow the input signal to rise above the first voltage level up to a threshold voltage that is above the source voltage sufficient to meet the logic switching threshold yet below the maximum voltage limit.

摘要翻译： 一种用于包括第一和第二通过装置和保护控制电路的接收器的过电压保护电路。 接收机使用基于低电压电平源电压的开关阈值来检测高电压电平输入信号的状态。 接收器在低电平和高电平之间具有最大电压限制。 第一通过器件将输入信号传递到低于源极电压的第一电压电平。 第二通道装置与第一通道装置并联有效耦合。 保护控制电路控制第二通过器件以允许输入信号升高到高于第一电压电平，直到高于源极电压的阈值电压足以满足逻辑开关阈值但低于最大电压限制。

公开(公告)号：US20050055538A1

公开(公告)日：2005-03-10

申请号：US10730168

申请日：2003-12-06

申请人： James Lundberg

发明人： James Lundberg

IPC分类号： G06F15/00 ,  H03K19/096

CPC分类号： H03K19/0963

摘要： A dynamic logic return-to-zero (RTZ) latching mechanism including a complementary pair of evaluation devices responsive to a clock signal, a dynamic evaluator, delayed inversion logic, and latching logic. The dynamic evaluator is coupled between the complementary pair of evaluation devices at a pre-charged node and evaluates a logic function based on at least one input data signal. The latching logic asserts the logic state of an output node based on the state of the pre-charged node during an evaluation period between an operative edge of the clock signal and the next edge of an evaluation complete signal, which is a delayed and inverted version of the clock signal. The output node is returned to zero between evaluation periods. A footless latching domino circuit may be added to convert the RTZ output to a registered output signal.

摘要翻译： 动态逻辑归零（RTZ）锁存机制包括响应于时钟信号的一对互补的评估装置，动态评估器，延迟反转逻辑和锁存逻辑。 动态评估器在预充电节点处耦合在互补的评估装置对之间，并基于至少一个输入数据信号来评估逻辑功能。 锁定逻辑在时钟信号的操作边缘与评估完成信号的下一个边缘之间的评估周期期间基于预充电节点的状态来断言输出节点的逻辑状态，该评估完成信号是延迟和反向版本 的时钟信号。 输出节点在评估周期之间返回到零。 可以添加一个无脚锁定多米诺骨牌电路，以将RTZ输出转换为已注册的输出信号。

公开(公告)号：US20070001778A1

公开(公告)日：2007-01-04

申请号：US11172375

申请日：2005-06-30

申请人： James Lundberg ,  Robert Zigler ,  For Lam

发明人： James Lundberg ,  Robert Zigler ,  For Lam

IPC分类号： H01P5/02

CPC分类号： H01Q1/002 ,  H01Q1/22

摘要： A system useful in providing communications with automatic data collection (ADC) devices employs an antenna located in a potentially hazardous environment, a radio circuit located in a non-hazardous environment, and a coupling apparatus to provide an interface between the antenna and the radio circuit that prevents electrical discharges from occurring in the potentially hazardous environment.

公开(公告)号：US20050248368A1

公开(公告)日：2005-11-10

申请号：US10834900

申请日：2004-04-28

申请人： Raymond Bertram ,  James Lundberg

发明人： Raymond Bertram ,  James Lundberg

IPC分类号： H03K19/096

CPC分类号： H03K19/0963

摘要： An apparatus and method are provided for accelerating the evaluated output of an P-domino latch. The apparatus includes evaluation P-logic, latching logic, keeper logic, and acceleration logic. The evaluation P-logic is coupled to a first N-channel device at a pre-charged node, and is configured to evaluate a logic function based on at least one input data signal. The latching logic is coupled and responsive to a clock signal and the pre-charged node. The latching logic controls the state of a latch node based on the state of the pre-charged node during an evaluation period between a first edge of said clock signal and a second edge of the clock signal. The latching logic otherwise presents a tri-state condition to the latch node. The keeper logic is coupled to the latch node. The keeper logic maintains the state of the latch node when the tri-state condition is presented, and provides a complementary state of the latch node at a complementary latch node. The acceleration logic is coupled and responsive to the pre-charged node and the complementary latch node, and is configured to control the state of an output node.

摘要翻译： 提供了一种用于加速P-domino闩锁的评估输出的装置和方法。 该装置包括评估P逻辑，锁存逻辑，保持器逻辑和加速度逻辑。 评估P逻辑在预充电节点处耦合到第一N沟道器件，并且被配置为基于至少一个输入数据信号来评估逻辑功能。 锁存逻辑被耦合并响应于时钟信号和预充电节点。 所述锁存逻辑在所述时钟信号的第一边缘和所述时钟信号的第二边沿之间的评估周期期间基于所述预充电节点的状态来控制锁存节点的状态。 闭锁逻辑否则向锁存节点呈现三态条件。 保持器逻辑耦合到锁存节点。 当呈现三态条件时，保持器逻辑维持锁存节点的状态，并且在互补锁存节点处提供锁存节点的互补状态。 加速度逻辑被耦合并响应于预充电节点和互补锁存节点，并且被配置为控制输出节点的状态。

公开(公告)号：US20070085560A1

公开(公告)日：2007-04-19

申请号：US11422001

申请日：2006-06-02

申请人： Darius Gaskins ,  James Lundberg

发明人： Darius Gaskins ,  James Lundberg

IPC分类号： H03K19/003

CPC分类号： G06F13/4086

摘要： The present invention provides a technique for enabling multiple devices to be interfaced together over a bus that requires dynamic impedance controls. In one embodiment, an apparatus is provided for enabling a multi-device environment on a bus, where the bus requires active termination impedance control. The apparatus includes a first node and multi-processor logic. The first node receives an indication that a corresponding device is at a physical end of the bus. The multi-processor logic is coupled to the first node. The multi-processor logic controls how a second node is driven according to the indication, where the second node is coupled to the bus.

摘要翻译： 本发明提供了一种使多个设备能够通过需要动态阻抗控制的总线连接在一起的技术。 在一个实施例中，提供了一种用于在总线上实现多设备环境的装置，其中总线需要主动终端阻抗控制。 该装置包括第一节点和多处理器逻辑。 第一节点接收到相应设备处于总线的物理端的指示。 多处理器逻辑耦合到第一节点。 多处理器逻辑控制如何根据第二节点耦合到总线的指示来驱动第二节点。

公开(公告)号：US20060033534A1

公开(公告)日：2006-02-16

申请号：US11251517

申请日：2005-10-14

申请人： James Lundberg ,  Raymond Bertram

发明人： James Lundberg ,  Raymond Bertram

IPC分类号： H03K19/096

CPC分类号： H03K19/0963

摘要： An N-domino latch includes a domino stage, a write stage, an inverter, a high keeper path, a low keeper path, and an output stage. The domino stage is coupled to an approximately symmetric clock signal. The domino stage evaluates a logic function according to the states of at least one data signal and the approximately symmetric clock signal, where the domino stage pre-charges a pre-charged node high when the approximately symmetric clock signal is low, and discharges the pre-charged node to a low state if the logic function evaluates when the approximately symmetric clock signal is high, and keeps the pre-charged node high if the logic function fails to evaluate when the approximately symmetric clock signal is high, where a latching state of the at least one data signal is provided to the domino stage when the approximately symmetric clock signal is high.

摘要翻译： N多米诺锁存器包括多米诺骨牌阶段，写阶段，逆变器，高保持者路径，低守护者路径和输出阶段。 多米诺骨牌阶段耦合到近似对称的时钟信号。 多米诺骨牌阶段根据至少一个数据信号和近似对称的时钟信号的状态来评估逻辑功能，其中，当近似对称的时钟信号为低时，多米诺舞台预充电节点为高电平，并且放电预先 如果逻辑功能在大致对称的时钟信号为高时评估逻辑功能，并且如果逻辑功能未能评估何时近似对称的时钟信号为高，则将预充电节点保持为高电平，其中锁定状态 当大致对称的时钟信号为高时，至少一个数据信号被提供给多米诺骨牌阶段。