公开(公告)号：US20180359082A1

公开(公告)日：2018-12-13

申请号：US15617940

申请日：2017-06-08

Applicant: NXP B.V.

Inventor： Joppe Willem BOS ,  Jan HOOGERBRUGGE ,  Marc JOYE ,  Wilhelmus Petrus Adrianus Johannus MICHIELS

IPC: H04L9/06 ,  H04L9/30 ,  G09C1/00

CPC classification number: H04L9/0631 ,  G09C1/00 ,  H04L9/002 ,  H04L9/30 ,  H04L2209/12 ,  H04L2209/16

Abstract: A method for producing a white-box implementation of a cryptographic function using garbled circuits, including: producing, by a first party, a logic circuit implementing the cryptographic function using a plurality of logic gates and a plurality of wires; garbling the produced logic circuit, by the first party, including garbling the plurality of logic gates and assigning two garbled values for each of the plurality of wires; and providing a second party the garbled logic circuit and a first garbled circuit input value.