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    COMPILATION SCHEME FOR TAGGED GLOBAL VARIABLES
    1.
    发明申请
    COMPILATION SCHEME FOR TAGGED GLOBAL VARIABLES 有权

    公开(公告)号：US20210182175A1

    公开(公告)日：2021-06-17

    申请号：US16715656

    申请日：2019-12-16

    Applicant: NXP B.V.

    Inventor： Jan HOOGERBRUGGE ,  Marcel MEDWED

    IPC: G06F11/36 ,  G06F8/41

    Abstract: A system and method for accessing a tagged global variable in software, including: randomly generating tags for global variables in the software; tagging the global variables with the random tags; creating a pointer to each global variable with the random tags in unused bits of the pointer wherein the pointer points to the associated global variable; accessing one global variable indirectly using the tagged pointer; determining whether tag on the accessed global variable matches the tag on the accessed pointer; and indicating a fault when the tag on the accessed global variable does not match the tag on the accessed pointer.

    CLOCK CONTROL CIRCUIT AND METHOD
    2.
    发明申请
    CLOCK CONTROL CIRCUIT AND METHOD 有权
    时钟控制电路及方法

    公开(公告)号：US20140317433A1

    公开(公告)日：2014-10-23

    申请号：US14244757

    申请日：2014-04-03

    Applicant: NXP B.V.

    Inventor： Hamed FATEMI ,  Rinze Ida Mechtildis Peter MEIJER ,  Ghiath AL-KADI ,  Surendra GUNTUR ,  Jan HOOGERBRUGGE

    IPC: G06F1/06

    CPC classification number: G06F1/06 ,  G06F1/04 ,  G06F1/08 ,  G06F9/38 ,  G06F9/3869 ,  G06F11/00

    Abstract: This invention provides a clock control circuit, which can be added to any pipeline-processor to solve timing problems arising from variations due to process outcome and environmental conditions. Critical instructions are detected (instructions that exercise critical paths) in conjunction with environmental sensing (such as process, temperature and voltage). This information is used to control cycle stealing.

    Abstract translation: 本发明提供一种时钟控制电路，其可以被添加到任何流水线处理器以解决由于过程结果和环境条件引起的变化引起的定时问题。 检测到关键指令（执行关键路径的指令）与环境感测（如过程，温度和电压）相结合。 此信息用于控制周期窃取。

    PROGRAM CODE PROTECTION IN A DATA PROCESSING SYSTEM
    3.
    发明申请
    PROGRAM CODE PROTECTION IN A DATA PROCESSING SYSTEM 有权

    公开(公告)号：US20210382740A1

    公开(公告)日：2021-12-09

    申请号：US16893628

    申请日：2020-06-05

    Applicant: NXP B.V.

    Inventor： Jan HOOGERBRUGGE

    IPC: G06F9/455 ,  G06F12/02 ,  G06F12/1018 ,  G06F12/14 ,  G06F12/0882

    Abstract: A method is provided in a data processing system having second level address translation (SLAT) controlled by a hypervisor. In the method, hashes of all memory pages accessible by a guest OS are stored (set S). Also, hashes of all memory pages previously accessed by the guest OS are stored (set T). When the guest OS attempts an access to a memory page having executable code for which it does not have permission, an exception is generated. A hash of the memory page is compared with the hashes of set T and set S. If there is not a match within set T, then the guest OS has never attempted the requested operation before and suspicious behavior is reported. If there is not a match within set S, the requested operation is reported as illegal. In another embodiment, the memory page may be encrypted to prevent the guest OS from reading the memory page.

    DATA PROCESSING SYSTEM AND METHOD FOR ACCESSING DATA IN THE DATA PROCESSING SYSTEM
    4.
    发明申请
    DATA PROCESSING SYSTEM AND METHOD FOR ACCESSING DATA IN THE DATA PROCESSING SYSTEM 有权

    公开(公告)号：US20220114002A1

    公开(公告)日：2022-04-14

    申请号：US17066179

    申请日：2020-10-08

    Applicant: NXP B.V.

    Inventor： Jan HOOGERBRUGGE ,  Wilhelmus Petrus Adrianus Johannus MICHIELS

    IPC: G06F9/455 ,  G06F21/79 ,  H04L9/06

    Abstract: A data processing system has a processor, a system memory, and a hypervisor. The system memory stores program code and data in a plurality of memory pages. The hypervisor controls SLAT (second level address translation) read, write, and execute access rights of the plurality of memory pages. A portion of the plurality of memory pages are classified as being in a secure enclave portion of the system memory and a portion is classified as being in an unsecure memory area. The portion of the memory pages classified in the secure enclave is encrypted and a hash is generated for each of the memory pages. During an access of a memory page, the hypervisor determines if the accessed memory page is in the secure enclave or in the unsecure memory area based on the hash. In another embodiment, a method for accessing a memory page in the secure enclave is provided.

    PERIPHERAL BASED MEMORY SAFETY SCHEME FOR MULTI-CORE PLATFORMS
    5.
    发明申请
    PERIPHERAL BASED MEMORY SAFETY SCHEME FOR MULTI-CORE PLATFORMS 审中-公开

    公开(公告)号：US20200174694A1

    公开(公告)日：2020-06-04

    申请号：US16206066

    申请日：2018-11-30

    Applicant: NXP B.V.

    Inventor： Marcel MEDWED ,  Jan HOOGERBRUGGE ,  Ventzislav NIKOV

    IPC: G06F3/06 ,  G06F13/24

    Abstract: A computing system using low-fat pointers, including: a memory configured to be accessed by the low-fat pointers; a processing core configured to access the memory; an interrupt controller configured to receive interrupts and to communicate interrupts to processes running on the processing core; and a memory safety peripheral configured to receive a pointer request, wherein the pointer is a low-fat pointer and to verify that the pointer request is within required memory bounds

    PROBABILISTIC MEMORY SAFETY USING CRYPTOGRAPHY
    7.
    发明申请
    PROBABILISTIC MEMORY SAFETY USING CRYPTOGRAPHY 审中-公开

    公开(公告)号：US20200380140A1

    公开(公告)日：2020-12-03

    申请号：US16427977

    申请日：2019-05-31

    Applicant: NXP B.V.

    Inventor： Marcel MEDWED ,  Jan HOOGERBRUGGE ,  Ventzislav NIKOV ,  Asier GOIKOETXEA YANCI

    IPC: G06F21/60 ,  G06F21/62 ,  G06F17/18

    Abstract: A chip for securing storage of information includes a manager to access a pointer and a cipher engine to decrypt stored data. The pointer includes a first area and a second area. The first area includes an address indicating a storage location of the data and the second area includes a safety tag. The cipher engine decrypts the data output from the storage location based on a key and the safety tag in the second area of the pointer. These and other operations may be performed based on metadata that indicate probabilities that a correct safety tag was used to decrypt the data. in another embodiment, the manager may be replaced with an L1 cache.

    USING WHITE-BOX IN A LEAKAGE-RESILIENT PRIMITIVE
    8.
    发明申请
    USING WHITE-BOX IN A LEAKAGE-RESILIENT PRIMITIVE 审中-公开

    公开(公告)号：US20190132116A1

    公开(公告)日：2019-05-02

    申请号：US15795890

    申请日：2017-10-27

    Applicant: NXP B.V.

    Inventor： Wilhelmus Petrus Adrianus Johannus MICHIELS ,  Marcel MEDWED ,  Jan HOOGERBRUGGE ,  Ventzislav NIKOV ,  Bruce MURRAY ,  Joppe Willem BOS

    IPC: H04L9/06 ,  H04L9/14

    Abstract: A method for implementing a pseudo-random function (PRF) using a white-box implementation of a cryptographic function in N rounds, including: receiving an input to the PRF; receiving a cryptographic key in a first round; encrypting, using the white-box implementation of the cryptographic function and the cryptographic key, an input message that is one of M possible input messages based upon a portion of the input to produce a first output; for each succeeding round: encrypting, using the white-box implementation of the cryptographic function and an ith cryptographic key, further input messages that are one of M possible input messages based upon a further portion of the input to produce an ith output, wherein the ith cryptographic key is the output from the preceding round, wherein the white-box implementation of the cryptographic function only produces a correct output for the M possible input messages and produces an incorrect output for input messages that are not one of the M possible input messages.

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