公开(公告)号：US20230101091A1

公开(公告)日：2023-03-30

申请号：US17449533

申请日：2021-09-30

Applicant: NXP B.V.

Inventor： Marco Jan Gerrit Bekooij

IPC: G01S7/41 ,  G01S7/292 ,  G01S13/36

Abstract: A snapshot comprises a plurality of signals is received where each of the plurality of signals reflected from a respective source and received by an antenna array. A first DoA estimator determines, based on the received snapshot, a plurality of DoAs, the plurality of DoAs comprising a respective DoA for each of the plurality of signals. A reliability of the plurality of DoAs is measured. In response to the reliability of the plurality of the DoAs exceeding a threshold, at least one of the plurality of the DoAs determined by the first DoA estimator is output. In response to the reliability of the plurality of the DoAs not exceeding the threshold, a second DoA estimator determines based on the received snapshot a second plurality of DoAs comprising a respective DoA of each of the plurality of signals and outputs at least one of the second plurality of DoAs.

公开(公告)号：US11513206B2

公开(公告)日：2022-11-29

申请号：US16900580

申请日：2020-06-12

Applicant: NXP B.V.

Inventor： Marco Jan Gerrit Bekooij ,  René Geraets

IPC: G01S13/04 ,  G01S7/02 ,  G01S7/35 ,  G01S13/34

Abstract: Exemplary aspects are directed to circuitry that assesses and differentiates a set of targeted data and updates a high-level bin with a numerical value indicating the number of data elements that compared successfully with a predefined value range defined for each bin. A cumulative sum of the high-level bins may then be calculated. Following, a target threshold may be compared to the cumulative sum at each bin and then providing an indication upon discovering a cumulative sum exceeding the threshold. The targeted data may be further refined by changing (through circuitry or other intervention) the predefined range values and then reprocessing the targeted data.

公开(公告)号：US11301542B2

公开(公告)日：2022-04-12

申请号：US16413162

申请日：2019-05-15

Applicant: NXP B.V.

Inventor： Marco Jan Gerrit Bekooij

IPC: G06F17/14 ,  G06F7/523

Abstract: An apparatus includes front-end circuitry to receive radar wave signals and a fast fourier transforms (FFT) signal processor. The FFT signal processor includes multiplication logic circuitry and other logic circuitry. The FFT signal processor derives doppler information from the radar wave signals by operating on a digital stream of input data representing the radar wave signals including using the multiplication logic circuitry to perform multiplication operations on first data in the digital stream while the first data is represented in a signed magnitude form, and using the other logic circuitry to perform other mathematical operations on second data in the digital stream while the second data is represented in a two's complement form.