Method and device for generating a random signal and digital-to-analog converting systems using same
    11.
    发明授权
    Method and device for generating a random signal and digital-to-analog converting systems using same 失效
    用于产生随机信号的方法和装置以及使用其的数模转换系统

    公开(公告)号:US06337643B1

    公开(公告)日:2002-01-08

    申请号:US09786349

    申请日:2001-03-12

    CPC classification number: G06F1/02 G06F7/58 G06F7/602 G06F2101/14 H03M1/0641

    Abstract: A process and device for generation of a random signal, and a digital-analog conversion system using such a random signal. The process includes a first noise generation step, a second noise filtering step to obtain a signal x(t) with a predetermined spectral envelope H(f), a third step in which a non-linear function g is applied to the signal x(t) in order to give a signal y(t) similar to a predetermined amplitudes histogram f(y), the function g being defined by the following relation: y = g ⁡ ( x ) = α ⁢ ∫ 0 x ⁢ P ⁡ ( u ) f ⁡ ( u ) ⁢ ⅆ u where the function P is the histogram of the signal x(t) to which the third step is applied, and a fourth step in which a pulse response filtering w(t) is applied to the signal y(t) to correct its spectral envelope and obtain an output signal s(t) with a predetermined spectral envelope H(f). The pulse response w(t) is the inverse Fourier transform of a frequency function W obtained by dividing the function H(f) by the modulus Y2(f) of the Fourier transform of the signal y(t). Such a process, device, and system may find particular application to a direct digital frequency synthesis, such as in radar or instrumentation applications.

    Abstract translation: 用于产生随机信号的处理和装置,以及使用这种随机信号的数模转换系统。 该处理包括第一噪声产生步骤,第二噪声滤波步骤,以获得具有预定频谱包络H(f)的信号x(t);第三步骤,其中非线性函数g被施加到信号x( 为了给出类似于预定幅度直方图f(y)的信号y(t),函数g由以下关系定义:其中函数P是信号x(t)的直方图,其中, 应用第三步骤,第四步骤,对信号y(t)施加脉冲响应滤波w(t)以校正其频谱包络并获得具有预定频谱包络H(f)的输出信号s(t) )。 脉冲响应w(t)是通过将函数H(f)除以信号y(t)的傅里叶变换的模数Y2(f)而获得的频率函数W的傅立叶逆变换。 这样的过程,设备和系统可以发现特定应用于直接数字频率合成,例如在雷达或仪器应用中。

    Fractional phase-locked loop coherent frequency synthesizer
    12.
    发明授权
    Fractional phase-locked loop coherent frequency synthesizer 失效
    分数锁相环相干频率合成器

    公开(公告)号:US6107843A

    公开(公告)日:2000-08-22

    申请号:US70157

    申请日:1998-04-30

    CPC classification number: H03L7/1976

    Abstract: Present-day single or multiple fractional phase-locked loop frequency synthesizers are not phase coherent for they use a digital accumulator modulo a number P with a variable increment K, whose state is a function of the history of the change in values that have been imposed on the increment. This lack of phase coherence rules out the use of these synthesizers in certain fields such as that of Doppler radars. A novel type of single or multiple fractional phase-locked loop frequency synthesizer that is coherent in phase is proposed herein. This type of synthesizer comprises one or more counters with an increment of one, having their rate set by the reference oscillator of the synthesizer and being used in phase memories to enable changes in the increment or increments following a change in the fractional division ratio at instants that are synchronous with the reference oscillator.

    Abstract translation: 现在的单个或多个分数锁相环频率合成器不是相位相干的,因为它们使用具有可变增量K的数字模数P的数字累加器,其状态是已经施加的值的变化的历史的函数 在增量上。 这种缺乏相位一致性排除了在某些领域(如多普勒雷达)中使用这些合成器。 本文提出了一种新颖类型的单相或多分相锁相环频率合成器,其相位相干。 这种类型的合成器包括一个或多个增量为1的计数器,其速率由合成器的参考振荡器设置,并且用于相位存储器,以使得在时刻的分数分数比的变化之后可以改变增量或增量 与参考振荡器同步。

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