Image sensor apparatus and method capable of rapidly reading out and processing pixel voltages of pixel array

    公开(公告)号:US11012653B2

    公开(公告)日:2021-05-18

    申请号:US16601541

    申请日:2019-10-14

    Abstract: A method of image sensor apparatus includes: providing pixel array having pixel units arranged in M rows and N columns; providing N parallel column readout circuits each being arranged for reading out pixel data of one corresponding column; disposing a horizontal shift register in row direction coupled to the N parallel column readout circuits, to receive a pulse signal and a clock signal, sequentially shift a phase of the pulse signal according to the clock signal, and scan a corresponding column according to the shifted phase of the pulse signal; and using a column select circuit having N latches to receive a power down digital control signal transmitted from a microcontroller wherein the power down digital control signal is used to disable at least one column readout circuit to enable and select a portion of the set of N parallel column readout circuits.

    IMAGE SENSOR APPARATUS AND METHOD CAPABLE OF RAPIDLY READING OUT AND PROCESSING PIXEL VOLTAGES OF PIXEL ARRAY

    公开(公告)号:US20210112215A1

    公开(公告)日:2021-04-15

    申请号:US16601541

    申请日:2019-10-14

    Abstract: A method of image sensor apparatus includes: providing pixel array having pixel units arranged in M rows and N columns; providing N parallel column readout circuits each being arranged for reading out pixel data of one corresponding column; disposing a horizontal shift register in row direction coupled to the N parallel column readout circuits, to receive a pulse signal and a clock signal, sequentially shift a phase of the pulse signal according to the clock signal, and scan a corresponding column according to the shifted phase of the pulse signal; and using a column select circuit having N latches to receive a power down digital control signal transmitted from a microcontroller wherein the power down digital control signal is used to disable at least one column readout circuit to enable and select a portion of the set of N parallel column readout circuits.

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