公开(公告)号：US5898905A

公开(公告)日：1999-04-27

申请号：US582743

申请日：1996-01-04

申请人： Christopher Aldridge ,  Pranesh Sinha

发明人： Christopher Aldridge ,  Pranesh Sinha

IPC分类号： H01L23/31 ,  H04B17/00

CPC分类号： H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H04B17/16 ,  H04B17/29 ,  H01L2924/0002

摘要： A baseband simulation system is disclosed for testing an RF subsystem of a communication device, such as a cellular telephone, cordless telephone, etc. A preferred embodiment has a computer connected to an interface card which in turn is connected to a baseband simulation subsystem. The baseband simulation subsystem is connected to the RF subsystem under test. The baseband simulation subsystem includes three ports: a timing and control (TAC) port, an IQ port, and general purpose input output (GPIO) port. The TAC port receives a master clock signal from an external source and generates plural clocks therefrom. The IQ and GPIO ports receives at least one of these plural clocks. In a transmit mode, in response to one or more of the clocks generated by the TAC port, the IQ port retrieves from its memory prestored discrete I and Q samples and reconstructs therefrom arbitrary transmit analog i and q signals which are provided to the RF subsystem under test. In a receive mode, the IQ port receives analog i and q signals from the RF subsystem. The IQ port, in response to one or more clocks generated by the TAC port, converts the received analog i and q signals receive discrete I and Q samples. These receive discrete I and Q samples are transferred via the PCIF to the PC for analyzing the ability of the RF subsystem under test to modulate the inputted transmit analog i and q signals on one or more RF carrier signals and to demodulate the RF carrier signals to output the receive analog i and q signals. The GPIO port exchanges auxiliary discrete data with the PC and auxiliary analog signals with the RF subsystem under test.

摘要翻译： 公开了用于测试诸如蜂窝电话，无绳电话等的通信设备的RF子系统的基带模拟系统。优选实施例具有连接到接口卡的计算机，该接口卡又连接到基带模拟子系统。 基带仿真子系统连接到正在测试的RF子系统。 基带模拟子系统包括三个端口：定时和控制（TAC）端口，IQ端口和通用输入输出（GPIO）端口。 TAC端口从外部源接收主时钟信号并从其产生多个时钟信号。 IQ和GPIO端口至少接收到一个这些多个时钟。 在发送模式中，响应于由TAC端口产生的时钟中的一个或多个时钟，IQ端口从其存储器中检索预存储的离散I和Q采样，并从其中重构提供给RF子系统的任意发射模拟i和q信号 被测试。 在接收模式下，IQ端口从RF子系统接收模拟i和q信号。 IQ端口响应于由TAC端口产生的一个或多个时钟，转换所接收的模拟i和q信号接收离散的I和Q采样。 这些接收离散的I和Q样本通过PCIF传送到PC，用于分析被测RF射频子系统在一个或多个RF载波信号上调制输入的发射模拟i和q信号的能力，并将RF载波信号解调为 输出接收模拟i和q信号。 GPIO端口与PC和辅助模拟信号交换辅助离散数据，并与RF子系统进行测试。