公开(公告)号：US20220384115A1

公开(公告)日：2022-12-01

申请号：US17818205

申请日：2022-08-08

Applicant: Presidio Components, Inc.

Inventor： Hung Van Trinh ,  Alan Devoe ,  Lambert Devoe

IPC: H01G4/30 ,  H01G4/12 ,  H01G4/35 ,  H01G4/012

Abstract: A monolithic ceramic capacitor has a plurality of dielectric layers and a plurality of conductive layers sintered together to form a substantially monolithic ceramic body. The ceramic body defines at least one void between the dielectric and conductive layers. The void is at least partially enclosed within the ceramic body and bounded by at least a portion of a dielectric layer, a first conductive layer, and a second conductive layer. Within the dielectric body, the first and second conductive layers are connected in a nonconductive manner.

公开(公告)号：US10262803B1

公开(公告)日：2019-04-16

申请号：US15728120

申请日：2017-10-09

Applicant: Presidio Components, Inc.

Inventor： Hung Van Trinh ,  Alan Devoe

IPC: H01G4/35 ,  H01G4/30 ,  H01G4/005 ,  H01G4/012

Abstract: A multilayer chip capacitor includes electrodes comprised of numerous, closely spaced conductive layers interposed within a dielectric laminate. Adjacent conductive layers are essentially non-overlapping, so that fringe capacitance between opposing electrodes provides substantially all of the capacitance. The conductive layers may be shaped to form a non-planer boundary between electrodes. An additional high frequency integrated capacitor is formed from external electrode plates. The non-planar electrode boundary principle is also applied to discoidal capacitors in the form of a non-concentric electrode boundary.