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公开(公告)号：US20170243375A1
公开(公告)日：2017-08-24
申请号：US15047472
申请日：2016-02-18
Applicant: QUALCOMM Incorporated
Inventor： Usame Ceylan , Vineet Goel , Juraj Obert , Liang Li
IPC: G06T11/00
CPC classification number: G06T11/001 , G06T15/005
Abstract: Techniques are described for using a texture unit to perform operations of a shader processor. Some operations of a shader processor are repeatedly executed until a condition is satisfied, and in each execution iteration, the shader processor accesses the texture unit. Techniques are described for the texture unit to perform such operations until the condition is satisfied.
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12.发明授权公开(公告)号：US11790478B2
公开(公告)日：2023-10-17
申请号：US16984024
申请日：2020-08-03
Applicant: QUALCOMM Incorporated
Inventor： Liang Li , Elina Kamenetskaya , Andrew Evan Gruber
CPC classification number: G06T1/20 , G06F9/3001 , G06F9/30032 , G06F9/30145 , G06F9/5066 , G06F17/142 , G06F17/16 , G06T15/005
Abstract: The present disclosure relates to methods and apparatus for mapping a source location of input data for processing by a graphics processing unit. The apparatus can configure a processing element of the graphics processing unit with a predefined rule for decoding a data source parameter for executing a task by the graphics processing unit. Moreover, the apparatus can store the parameter in local storage of the processing element and configure the processing element to decode the parameter according to the at least one predefined rule to determine a source location of the input data and at least one relationship between invocations of the task. The apparatus can also load, to the local storage of the processing element, the input data from a plurality of memory addresses of the source location determined by the parameter. A one logic unit can then execute the task on the loaded input data.
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公开(公告)号：US20210104078A1
公开(公告)日：2021-04-08
申请号：US16591450
申请日：2019-10-02
Applicant: QUALCOMM Incorporated
Inventor： Yadong Wang , Himanshu Govil , Bagus Prasetyo Wibowo , Raghavendra Nagaraj , Liang Li , Elina Kamenetskaya
Abstract: Methods, systems, and devices for image processing are described. A device may support various filtering models relating to multidimensional graphics. The device may identify a target texel having a texel coordinate in an image, determine a set of neighboring texels based on the texel coordinate of the target texel, determine color values of multiple neighboring texels of the set of neighboring texels, compare the color values of the multiple neighboring texels of the set of neighboring texels, and process the target texel based on the comparing. In processing the target texel, the device may determine that the multiple neighboring texels may have same color values based on the comparing. The device may bypass a filtering operation on the target texel based on the multiple neighboring texels having the same color values. In an example of bypassing the filtering operation, the device may maintain a color value of the target texel.
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公开(公告)号：US20180293761A1
公开(公告)日：2018-10-11
申请号：US16006502
申请日：2018-06-12
Applicant: QUALCOMM Incorporated
Inventor： Usame Ceylan , Vineet Goel , Juraj Obert , Liang Li
CPC classification number: G06T11/001 , G06T15/005
Abstract: Techniques are described for using a texture unit to perform operations of a shader processor. Some operations of a shader processor are repeatedly executed until a condition is satisfied, and in each execution iteration, the shader processor accesses the texture unit. Techniques are described for the texture unit to perform such operations until the condition is satisfied.
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公开(公告)号：US20170316540A1
公开(公告)日：2017-11-02
申请号：US15141519
申请日：2016-04-28
Applicant: QUALCOMM Incorporated
Inventor： Andrew Evan Gruber , Lin Chen , Liang Li , Chunhui Mei
CPC classification number: G06T1/20 , G06T1/60 , G06T15/005 , G06T15/04 , G06T15/80 , G06T2200/28
Abstract: A texture unit of a graphics processing unit (GPU) may receive a texture data. The texture unit may receive the texture data from the memory. The texture unit may also multiply, by a multiplier circuit of the texture unit, the texture data by at least one constant, where the constant is not associated with a filtering operation, and where the texture data comprises at least one texel. The texture unit may also output, by the texture unit, a result of multiplying the texture data by the at least one constant.
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Patent Agency Ranking
公开(公告)号：US09697580B2
公开(公告)日：2017-07-04
申请号：US14537589
申请日：2014-11-10
Applicant: QUALCOMM Incorporated
Inventor： Liang Li , Andrew Evan Gruber , Guofang Jiao , Zhenyu Qi , Gregory Steve Pitarys , Scott William Nolan
CPC classification number: G06T1/20 , G09G5/18 , G09G2330/022
Abstract: This disclosure describes an apparatus configured to process graphics data. The apparatus may include a fixed hardware pipeline configured to execute one or more functions on a current set of graphics data. The fixed hardware pipeline may include a plurality of stages including a bypassable portion of the plurality of stages. The apparatus may further include a shortcut circuit configured to route the current set of graphics data around the bypassable portion of the plurality of stages, and a controller positioned before the bypassable portion of the plurality of stages, the controller configured to selectively route the current set of graphics data to one of the shortcut circuit or the bypassable portion of the plurality of stages.
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公开(公告)号：US20160132987A1
公开(公告)日：2016-05-12
申请号：US14537589
申请日：2014-11-10
Applicant: QUALCOMM Incorporated
Inventor： Liang Li , Andrew Evan Gruber , Guofang Jiao , Zhenyu Qi , Gregory Steve Pitarys , Scott William Nolan
CPC classification number: G06T1/20 , G09G5/18 , G09G2330/022
Abstract: This disclosure describes an apparatus configured to process graphics data. The apparatus may include a fixed hardware pipeline configured to execute one or more functions on a current set of graphics data. The fixed hardware pipeline may include a plurality of stages including a bypassable portion of the plurality of stages. The apparatus may further include a shortcut circuit configured to route the current set of graphics data around the bypassable portion of the plurality of stages, and a controller positioned before the bypassable portion of the plurality of stages, the controller configured to selectively route the current set of graphics data to one of the shortcut circuit or the bypassable portion of the plurality of stages.
Abstract translation: 本公开描述了被配置为处理图形数据的装置。 该装置可以包括被配置为在当前图形数据集上执行一个或多个功能的固定硬件流水线。 固定硬件管线可以包括多个级，包括多个级的可旁路部分。 该装置还可以包括快速电路，其被配置为将当前图形数据集合围绕多个级的可旁路部分路由，以及位于多个级的可旁路部分之前的控制器，所述控制器被配置为选择性地路由当前集合 的图形数据提供给多个阶段的快捷电路或可旁路部分中的一个。
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公开(公告)号：US12254555B2
公开(公告)日：2025-03-18
申请号：US18194324
申请日：2023-03-31
Applicant: QUALCOMM Incorporated
Inventor： Liang Li , Andrew Evan Gruber
Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for single pass anti-ringing clamping enabled image processing. A graphics processor may perform a filtering operation on a set of texture samples. The graphics processor may select, during a single sampling operation, a minimum value and a maximum value associated with the set of texture samples during the performance of the filtering operation on the set of texture samples. The graphics processor may adjust, during the single sampling operation, a value of a filtered texture sample associated with the set of texture samples based on the minimum value and the maximum value. The graphics processor may output an indication of the adjusted value of the filtered texture sample.
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19.发明授权公开(公告)号：US12229866B2
公开(公告)日：2025-02-18
申请号：US18155679
申请日：2023-01-17
Applicant: QUALCOMM Incorporated
Inventor： Elina Kamenetskaya , Liang Li , Jonathan Wicks , Samuel Benjamin Holmes
Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a graphics processing unit (GPU). The apparatus may obtain a first indication of a first image including a set of first image sections with a plurality of first subsections and a second indication of a second image including a set of second image sections with a plurality of second subsections. The apparatus may also compare one first image section with one second image section. Further, the apparatus may calculate a magnitude of difference between one first subsection and each of the multiple second subsections. The apparatus may also output a third indication of at least one of: (1) a lowest magnitude of difference between the one first subsection and each of the multiple second subsections or (2) a set of coordinates for a second subsection that corresponds to the lowest magnitude of difference.
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公开(公告)号：US10417791B2
公开(公告)日：2019-09-17
申请号：US16006502
申请日：2018-06-12
Applicant: QUALCOMM Incorporated
Inventor： Usame Ceylan , Vineet Goel , Juraj Obert , Liang Li
Abstract: Techniques are described for using a texture unit to perform operations of a shader processor. Some operations of a shader processor are repeatedly executed until a condition is satisfied, and in each execution iteration, the shader processor accesses the texture unit. Techniques are described for the texture unit to perform such operations until the condition is satisfied.
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