公开(公告)号：US20250098267A1

公开(公告)日：2025-03-20

申请号：US18469473

申请日：2023-09-18

Applicant: QUALCOMM Incorporated

Inventor： Yan SUN ,  Deepak SHARMA ,  Shreesh NARASIMHA

IPC: H01L29/417 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Disclosed are techniques for a semiconductor structure. In an aspect, a semiconductor structure includes a gate stack including a first gate structure and a second gate structure offset in a first direction. The semiconductor structure includes a first source/drain (S/D) structure adjacent the first gate structure, a second S/D structure adjacent the second gate structure, a first backside conductive structure in contact with the first S/D structure, and a second backside conductive structure in contact with the second S/D structure. The semiconductor structure includes a third backside conductive structure disposed in a back portion of the semiconductor structure opposing a front portion of the semiconductor structure, extending along a second direction, and in contact with the first backside conductive structure and the second backside conductive structure.

公开(公告)号：US20250096075A1

公开(公告)日：2025-03-20

申请号：US18469501

申请日：2023-09-18

Applicant: QUALCOMM Incorporated

Inventor： Shreesh NARASIMHA ,  Yan SUN ,  Yandong GAO ,  Peijie FENG

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H10B10/00

Abstract: In an aspect, a semiconductor memory cell comprises gate structures separated by source or drain (S/D) structures, a frontside (FS) inter-layer dielectric (FS-ILD) layer above the gate and S/D structures, FS metal zero (FM0) interconnects above the FS-ILD layer, a backside (BS) inter-layer dielectric (BS-ILD) layer below the gate and S/D structures, BS metal zero (BM0) interconnects below the BS-ILD layer, at least one FS source drain contact (FSDC) electrically connecting an FM0 interconnect to a top surface of an S/D structure, and at least one BS S/D contact (BSDC) electrically connecting a BMO interconnect to a bottom surface of an S/D structure. The semiconductor memory cell comprises NFETs and PFETs to form a cross-coupled inverter pair. For each inverter in the pair, one of VDD and VSS are provided by an FSDC and the other of VDD and VSS is provided by a BSDC.