公开(公告)号：US20140247678A1

公开(公告)日：2014-09-04

申请号：US14150659

申请日：2014-01-08

Applicant: RAMBUS INC.

Inventor： Adrian E. Ong ,  Fan Ho

IPC: G11C29/48

CPC classification number: G11C29/76 ,  G11C11/401 ,  G11C11/4085 ,  G11C29/027 ,  G11C29/04 ,  G11C29/12 ,  G11C29/4401 ,  G11C29/48 ,  G11C29/78 ,  G11C29/789 ,  G11C29/802 ,  G11C2229/743

Abstract: A controller including a non-volatile memory to store a repair address, and a memory control unit operatively coupled with the non-volatile memory. The memory control unit comprising a memory test function configured to detect a malfunctioning address of primary data storage elements within a memory device. The memory device being another semiconductor device separate from the controller. The memory test function configured to store the repair address in the non-volatile memory, the repair address indicating the malfunctioning address of the primary data storage element.

Abstract translation: 一种包括用于存储修复地址的非易失性存储器的控制器，以及与非易失性存储器可操作地耦合的存储器控​​制单元。 存储器控制单元包括存储器测试功能，其被配置为检测存储器设备内主要数据存储元件的故障地址。 存储器件是与控制器分开的另一个半导体器件。 所述存储器测试功能被配置为将所述修复地址存储在所述非易失性存储器中，所述修复地址指示所述主数据存储元件的故障地址。

公开(公告)号：US08670283B2

公开(公告)日：2014-03-11

申请号：US13872947

申请日：2013-04-29

Applicant: Rambus Inc.

Inventor： Adrian E. Ong ,  Fan Ho

IPC: G11C29/00

CPC classification number: G11C29/76 ,  G11C11/401 ,  G11C11/4085 ,  G11C29/027 ,  G11C29/04 ,  G11C29/12 ,  G11C29/4401 ,  G11C29/48 ,  G11C29/78 ,  G11C29/789 ,  G11C29/802 ,  G11C2229/743

Abstract: A controller including a non-volatile memory to store a repair address, and a memory control unit operatively coupled with the non-volatile memory. The memory control unit comprising a memory test function configured to detect a malfunctioning address of primary data storage elements within a memory device. The memory device being another semiconductor device separate from the controller. The memory test function configured to store the repair address in the non-volatile memory, the repair address indicating the malfunctioning address of the primary data storage element.

Abstract translation: 一种包括用于存储修复地址的非易失性存储器的控制器，以及与非易失性存储器可操作地耦合的存储器控​​制单元。 存储器控制单元包括存储器测试功能，其被配置为检测存储器设备内主要数据存储元件的故障地址。 存储器件是与控制器分开的另一个半导体器件。 所述存储器测试功能被配置为将所述修复地址存储在所述非易失性存储器中，所述修复地址指示所述主数据存储元件的故障地址。

公开(公告)号：US20220262718A1

公开(公告)日：2022-08-18

申请号：US17686331

申请日：2022-03-03

Applicant: Rambus Inc.

Inventor： Adrian E. Ong ,  Dong Sik Jeong

IPC: H01L23/50 ,  H01L21/48 ,  H01L23/538

Abstract: Methods, systems, and apparatus for reducing power consumption or signal distortions in a semiconductor device package. The semiconductor device package includes a semiconductor device, a first electric path, a second electric path, and an isolation element in the first electric path. The second electric path is electrically connected to the first electric path and a functional unit of the device. The isolation element separates an isolated portion in the first electric path from the second electric path, where the isolation element is configured to reduce current in the isolated portion when a signal is passing through the second electric path.

公开(公告)号：US20200273534A1

公开(公告)日：2020-08-27

申请号：US16870759

申请日：2020-05-08

Applicant: Rambus Inc.

Inventor： Adrian E. Ong ,  Fan Ho

IPC: G11C29/00 ,  G11C29/44 ,  G11C29/48 ,  G11C29/04 ,  G11C11/401 ,  G11C29/12 ,  G11C11/408 ,  G11C29/02

Abstract: A controller includes an internal memory to store an address and a memory control unit operatively coupled with the internal memory. The memory control unit includes logic to identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device being another semiconductor device separate from the controller, store the malfunctioning address in the internal memory, and transmit, to the external memory device, a command to initiate a repair of the malfunctioning address using redundant data storage elements and an indication of an address associated with the malfunctioning address.

公开(公告)号：US20190027231A1

公开(公告)日：2019-01-24

申请号：US16015941

申请日：2018-06-22

Applicant: Rambus Inc.

Inventor： Adrian E. Ong ,  Fan Ho

IPC: G11C29/00 ,  G11C29/44 ,  G11C11/408 ,  G11C29/48 ,  G11C11/401 ,  G11C29/12 ,  G11C29/04 ,  G11C29/02

Abstract: A controller includes an internal memory to store an address and a memory control unit operatively coupled with the internal memory. The memory control unit includes logic to identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device being another semiconductor device separate from the controller, store the malfunctioning address in the internal memory, and transmit, to the external memory device, a command to initiate a repair of the malfunctioning address using redundant data storage elements and an indication of an address associated with the malfunctioning address.

公开(公告)号：US09378849B2

公开(公告)日：2016-06-28

申请号：US14918148

申请日：2015-10-20

Applicant: RAMBUS INC.

Inventor： Adrian E. Ong ,  Fan Ho

IPC: G11C29/00 ,  G11C29/44 ,  G11C29/48 ,  G11C29/04 ,  G11C11/401 ,  G11C29/12

CPC classification number: G11C29/76 ,  G11C11/401 ,  G11C11/4085 ,  G11C29/027 ,  G11C29/04 ,  G11C29/12 ,  G11C29/4401 ,  G11C29/48 ,  G11C29/78 ,  G11C29/789 ,  G11C29/802 ,  G11C2229/743

Abstract: A controller includes an internal memory to store an address and a memory control unit operatively coupled with the internal memory. The memory control unit includes logic to identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device being another semiconductor device separate from the controller, store the malfunctioning address in the internal memory, and transmit, to the external memory device, a command to initiate a repair of the malfunctioning address using redundant data storage elements and an indication of an address associated with the malfunctioning address.

Abstract translation: 控制器包括用于存储地址的内部存储器和与内部存储器可操作地耦合的存储器控​​制单元。 存储器控制单元包括用于识别外部存储器件内的主要数据存储元件的故障地址的逻辑，外部存储器件是与控制器分离的另一个半导体器件，将故障地址存储在内部存储器中，并传输到外部存储器 存储器装置，使用冗余数据存储元件发起故障地址的修复的命令以及与故障地址相关联的地址的指示。

公开(公告)号：US12230350B2

公开(公告)日：2025-02-18

申请号：US18243054

申请日：2023-09-06

Applicant: Rambus Inc.

Inventor： Adrian E. Ong ,  Fan Ho

IPC: G11C29/00 ,  G11C11/401 ,  G11C11/408 ,  G11C29/02 ,  G11C29/04 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48

Abstract: A dynamic random access memory (DRAM) comprises a plurality of primary data storage elements, a plurality of redundant data storage elements, and circuitry to receive a first register setting command and initiate a repair mode in the DRAM in response to the first register setting command. The circuitry is further to receive an activation command, repair a malfunctioning row address in the DRAM, receive a precharge command, receive a second register setting command, terminate the repair mode in the DRAM in response to the second register setting command, receive a memory access request for data stored at the malfunctioning row address, and redirect the memory access request to a corresponding row address in the plurality of redundant data storage elements.

公开(公告)号：US11501848B2

公开(公告)日：2022-11-15

申请号：US17344155

申请日：2021-06-10

Applicant: Rambus Inc.

Inventor： Adrian E. Ong ,  Fan Ho

IPC: G11C29/04 ,  G11C29/00 ,  G11C29/44 ,  G11C29/48 ,  G11C11/401 ,  G11C29/12 ,  G11C11/408 ,  G11C29/02

Abstract: A controller includes an internal memory to store an address and a memory control unit operatively coupled with the internal memory. The memory control unit includes logic to identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device being another semiconductor device separate from the controller, store the malfunctioning address in the internal memory, and transmit, to the external memory device, a command to initiate a repair of the malfunctioning address using redundant data storage elements and an indication of an address associated with the malfunctioning address.

公开(公告)号：US20220238177A1

公开(公告)日：2022-07-28

申请号：US17720054

申请日：2022-04-13

Applicant: Rambus Inc.

Inventor： Adrian E. Ong ,  Fan Ho

IPC: G11C29/00 ,  G11C29/44 ,  G11C29/48 ,  G11C29/04 ,  G11C11/401 ,  G11C29/12 ,  G11C11/408 ,  G11C29/02

Abstract: A dynamic random access memory (DRAM) comprises a plurality of primary data storage elements, a plurality of redundant data storage elements, and circuitry to receive a first register setting command and initiate a repair mode in the DRAM in response to the first register setting command. The circuitry is further to receive an activation command, repair a malfunctioning row address in the DRAM, receive a precharge command, receive a second register setting command, terminate the repair mode in the DRAM in response to the second register setting command, receive a memory access request for data stored at the malfunctioning row address, and redirect the memory access request to a corresponding row address in the plurality of redundant data storage elements.

公开(公告)号：US11037652B2

公开(公告)日：2021-06-15

申请号：US16870759

申请日：2020-05-08

Applicant: Rambus Inc.

Inventor： Adrian E. Ong ,  Fan Ho

IPC: G11C29/00 ,  G11C29/44 ,  G11C29/48 ,  G11C29/04 ,  G11C11/401 ,  G11C29/12 ,  G11C11/408 ,  G11C29/02

Abstract: A controller includes an internal memory to store an address and a memory control unit operatively coupled with the internal memory. The memory control unit includes logic to identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device being another semiconductor device separate from the controller, store the malfunctioning address in the internal memory, and transmit, to the external memory device, a command to initiate a repair of the malfunctioning address using redundant data storage elements and an indication of an address associated with the malfunctioning address.