公开(公告)号：US20210167789A1

公开(公告)日：2021-06-03

申请号：US17262901

申请日：2019-07-30

Applicant: Rambus Inc.

Inventor： Kenneth C. DYER ,  Marcus VAN IERSSEL

IPC: H03M1/10 ,  H03M1/06

Abstract: Disclosed is a successive approximation register (SAR) analog to digital converter (ADC) that uses two or more comparators. This allows the output of one comparator to be latched while the other comparators are comparing and switching. Statistical measures are used to correct the offsets of one or more of the comparators. If a statistically significant mismatch in the number of 1's and 0's occurs in a subset of the bits, adjustments to the offsets of one or more of the comparators are made until there is roughly an equal number of 1 and 0 values. This can reduce or eliminate the need for dedicated offset correction cycles.

公开(公告)号：US20200007137A1

公开(公告)日：2020-01-02

申请号：US16441742

申请日：2019-06-14

Applicant: Rambus Inc.

Inventor： Marcus VAN IERSSEL ,  Dominic DICLEMENTE

IPC: H03M1/06 ,  H03M7/16

Abstract: A phase rotator receives control signals and thermometer coded signals that specifies the phase of an output signal. The phase rotator may be used, for example, by a clock and data recovery (CDR) circuit to continually rotate the phase of a clock to compensate for phase/frequency mismatches between received data and the clock. The control signals determine the phase quadrant (i.e., 0°-90°, 90°-180°, etc.) of the output signal. The thermometer coded signals determine the phase of the output signal within a quadrant by steering a set of bias currents between two or more nodes. The set of bias currents are selected to reduce the non-linearity between the thermometer coded value and the phase of the output signal.