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公开(公告)号：US20210336627A1
公开(公告)日：2021-10-28
申请号：US17315699
申请日：2021-05-10
Applicant: Rambus Inc.
Inventor： Masum HOSSAIN , Kenneth C. DYER , Nhat NGUYEN , Shankar TANGIRALA
Abstract: A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.
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公开(公告)号：US20210167789A1
公开(公告)日：2021-06-03
申请号：US17262901
申请日：2019-07-30
Applicant: Rambus Inc.
Inventor： Kenneth C. DYER , Marcus VAN IERSSEL
Abstract: Disclosed is a successive approximation register (SAR) analog to digital converter (ADC) that uses two or more comparators. This allows the output of one comparator to be latched while the other comparators are comparing and switching. Statistical measures are used to correct the offsets of one or more of the comparators. If a statistically significant mismatch in the number of 1's and 0's occurs in a subset of the bits, adjustments to the offsets of one or more of the comparators are made until there is roughly an equal number of 1 and 0 values. This can reduce or eliminate the need for dedicated offset correction cycles.
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公开(公告)号：US20230253974A1
公开(公告)日：2023-08-10
申请号：US18092564
申请日：2023-01-03
Applicant: Rambus Inc.
Inventor： Masum HOSSAIN , Kenneth C. DYER , Nhat NGUYEN , Shankar TANGIRALA
CPC classification number: H03M1/002 , H04L25/03038 , H04L25/03 , H03M1/007 , H03M1/145
Abstract: A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.
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公开(公告)号：US20220321138A1
公开(公告)日：2022-10-06
申请号：US17728607
申请日：2022-04-25
Applicant: Rambus Inc.
Inventor： Kenneth C. DYER , Marcus VAN IERSSEL
Abstract: Disclosed is a successive approximation register (SAR) analog to digital converter (ADC) that uses two or more comparators. This allows the output of one comparator to be latched while the other comparators are comparing and switching. Statistical measures are used to correct the offsets of one or more of the comparators. If a statistically significant mismatch in the number of 1's and 0's occurs in a subset of the bits, adjustments to the offsets of one or more of the comparators are made until there is roughly an equal number of 1 and 0 values. This can reduce or eliminate the need for dedicated offset correction cycles.
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