公开(公告)号：US11626876B2

公开(公告)日：2023-04-11

申请号：US17393844

申请日：2021-08-04

Applicant: Rambus Inc.

Inventor： Panduka Wijetunga ,  Dhiraj Kumar

IPC: H03K19/007 ,  H03K19/003

Abstract: Push-pull integrated circuit output drivers may interfere with communication by other entities on a bus when an integrated circuit is powered down. When there is no power and/or when the bonding pad is externally driven above the internal supply voltage, the substrate/body/well of the p-channel field effect transistor (PFET) of the output driver is biased to prevent its drain diode from becoming forward biased thereby preventing interference with communication on the bus. Also, when there is no power, driver is powered down or pull up is disabled, the gate of the driver PFET is driven to a voltage that ensures the driver PFET remains off when the bonding pad is externally driven above the internal supply voltage.

公开(公告)号：US20220385320A1

公开(公告)日：2022-12-01

申请号：US17742679

申请日：2022-05-12

Applicant: Rambus Inc.

Inventor： Panduka Wijetunga

IPC: H04B1/10 ,  H04B1/12

Abstract: A binary receiver combines a fast amplifier with a relatively slow amplifier for noise rejection. Both the fast and slow amplifiers employ hysteresis. The fast amplifier has relatively lower hysteresis, meaning that its sensitivity is a less effected by prior data values but more susceptible to glitch-induced errors. Conversely, the slow amplifier has relatively higher hysteresis and rejects glitches but introduces undesirable signal-propagation delays. A state machine taking input from both amplifiers allows the receiver to filter glitches without incurring a significant data-propagation delay.

公开(公告)号：US20220358989A1

公开(公告)日：2022-11-10

申请号：US17725026

申请日：2022-04-20

Applicant: Rambus Inc.

Inventor： Panduka Wijetunga ,  Aws Shallal ,  Joey M. Esteves

IPC: G11C11/4074

Abstract: A power-management integrated circuit (PMIC) is installed on a memory module to optimize power use among a collection of memory devices. The PMIC includes external power-supply nodes that receive relatively high and low supply voltages. Depending on availability, the PMIC uses one or both of these supply voltages to generate a managed supply voltage for powering the memory devices. The PMIC selects between operational modes for improved efficiency in dependence upon the availability of one or both externally provided supply voltages.

公开(公告)号：US20240395309A1

公开(公告)日：2024-11-28

申请号：US18734655

申请日：2024-06-05

Applicant: Rambus Inc.

Inventor： Panduka Wijetunga ,  Aws Shallal ,  Joey M. Esteves

IPC: G11C11/4074

Abstract: A power-management integrated circuit (PMIC) is installed on a memory module to optimize power use among a collection of memory devices. The PMIC includes external power-supply nodes that receive relatively high and low supply voltages. Depending on availability, the PMIC uses one or both of these supply voltages to generate a managed supply voltage for powering the memory devices. The PMIC selects between operational modes for improved efficiency in dependence upon the availability of one or both externally provided supply voltages.

公开(公告)号：US20240063835A1

公开(公告)日：2024-02-22

申请号：US18458435

申请日：2023-08-30

Applicant: Rambus Inc.

Inventor： Panduka Wijetunga

IPC: H04B1/10 ,  H04B1/12

CPC classification number: H04B1/1027 ,  H04B1/12 ,  H04B1/1018

Abstract: A binary receiver combines a fast amplifier with a relatively slow amplifier for noise rejection. Both the fast and slow amplifiers employ hysteresis. The fast amplifier has relatively lower hysteresis, meaning that its sensitivity is a less effected by prior data values but more susceptible to glitch-induced errors. Conversely, the slow amplifier has relatively higher hysteresis and rejects glitches but introduces undesirable signal-propagation delays. A state machine taking input from both amplifiers allows the receiver to filter glitches without incurring a significant data-propagation delay.

公开(公告)号：US20230198405A1

公开(公告)日：2023-06-22

申请号：US17989048

申请日：2022-11-17

Applicant: Rambus Inc.

Inventor： Gaurav Bawa ,  Panduka Wijetunga ,  Mo Zhang

IPC: H02M3/158 ,  H02M1/00 ,  G01R1/20

CPC classification number: H02M3/1582 ,  H02M1/0025 ,  G01R1/203

Abstract: An integrated circuit including a buck converter having an integrator and a shunt resistor is described. The buck converter may operate in a continuous conduction mode (CCM) and a discontinuous conduction mode (DCM). The integrator may be coupled to the buck converter to generate an output voltage based on adjustment of a detected voltage across a load of the buck converter within range of a reference voltage. The shunt resistor may be coupled to the integrator configured to maintain the output voltage of the integrator during the DCM.

公开(公告)号：US20230185351A1

公开(公告)日：2023-06-15

申请号：US18077881

申请日：2022-12-08

Applicant: Rambus Inc.

Inventor： Aws Shallal ,  Panduka Wijetunga

IPC: G06F1/3206 ,  G05F1/56

CPC classification number: G06F1/3206 ,  G05F1/56

Abstract: Disclosed are techniques for a power management integrated circuit (PMIC) to support a power-up sequence from a powered-down state to a powered-up state when both a main supply voltage and a backup supply voltage are present or when only the backup supply voltage is present. The PMIC may monitor the two supply voltages to identify the supply voltages that are present. The PMIC may be configured with a power-up initialization mode of operation through an EFUSE/MTP register, including a first bit to control power up of a voltage regulator of the PMIC with the main supply voltage or the backup supply voltage. Another bit may control power up of the voltage regulator with the backup supply voltage in the dual-supply or the single-supply configuration. The PMIC may execute one of four power-up sequences based on the monitored status of the supply voltages and the configured power-up initialization mode of operation.