公开(公告)号：US20230409205A1

公开(公告)日：2023-12-21

申请号：US18339812

申请日：2023-06-22

Applicant: Rambus Inc.

Inventor： Aws Shallal ,  Micheal Miller ,  Stephen Horn

IPC: G06F3/06 ,  G11C14/00 ,  G06F12/14 ,  G06F11/00 ,  G11C5/04 ,  G11C11/00 ,  G06F12/0802 ,  G06F13/16

CPC classification number: G06F3/0613 ,  G06F3/0611 ,  G11C14/0009 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/1441 ,  G06F11/00 ,  G11C5/04 ,  G11C11/005 ,  G06F3/065 ,  G06F3/0685 ,  G06F12/0802 ,  G06F13/1673 ,  G06F13/1668 ,  G11C7/1051

Abstract: Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode.

公开(公告)号：US11030118B2

公开(公告)日：2021-06-08

申请号：US15849507

申请日：2017-12-20

Applicant: Rambus Inc.

Inventor： Aws Shallal ,  Larry Grant Giddens ,  Sarvagya Kochak

IPC: G06F12/0862 ,  G06N20/00 ,  G06F12/14 ,  G06F3/06 ,  G06F21/79 ,  G06F21/57 ,  G06F9/4401

Abstract: In a memory module, encryption information is received from an external source and stored exclusively within a non-persistent storage element such that the encryption information is expunged from the memory module upon power loss. Write data is received and encrypted using the encryption information stored within the non-persistent storage element to produce encrypted data which is stored, in turn, within a nonvolatile storage of the memory module.

公开(公告)号：US20200034046A1

公开(公告)日：2020-01-30

申请号：US16535814

申请日：2019-08-08

Applicant: Rambus Inc.

Inventor： Aws Shallal ,  Michael Miller ,  Stephen Horn

IPC: G06F3/06 ,  G11C14/00 ,  G06F12/14 ,  G06F11/00 ,  G11C5/04 ,  G11C11/00 ,  G06F12/0802 ,  G06F13/16

Abstract: Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode.

公开(公告)号：US20190318783A1

公开(公告)日：2019-10-17

申请号：US16467619

申请日：2017-11-20

Applicant: Rambus Inc.

Inventor： Aws Shallal ,  Nigel Alvares ,  Sarvagya Kochak

IPC: G11C14/00 ,  G06F12/0804

Abstract: A system that includes a non-volatile memory subsystem having non-volatile memory. The system also includes a plurality of memory modules that are separate from the non-volatile memory subsystem. Each memory module can include a plurality of random access memory packages where each first random access memory package includes a primary data port and a backup data port. Each memory module can include a storage interface circuit coupled to the backup data ports of the random access memory packages. The storage interface circuit offloads data from the memory module in the event of a power loss by receiving data from the backup data ports of the random access memory packages and transmitting the data to the non-volatile memory subsystem.

公开(公告)号：US10379752B2

公开(公告)日：2019-08-13

申请号：US16042374

申请日：2018-07-23

Applicant: Rambus Inc.

Inventor： Aws Shallal ,  Michael Miller ,  Stephen Horn

IPC: G06F3/06 ,  G11C14/00 ,  G06F12/14 ,  G06F11/00 ,  G11C5/04 ,  G11C11/00 ,  G06F12/0802 ,  G06F13/16 ,  G11C7/10

Abstract: Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode.

公开(公告)号：US20250110540A1

公开(公告)日：2025-04-03

申请号：US18916160

申请日：2024-10-15

Applicant: Rambus Inc.

Inventor： Aws Shallal ,  Panduka Wijetunga

IPC: G06F1/3206 ,  G05F1/56

Abstract: Disclosed are techniques for a power management integrated circuit (PMIC) to support a power-up sequence from a powered-down state to a powered-up state when both a main supply voltage and a backup supply voltage are present or when only the backup supply voltage is present. The PMIC may monitor the two supply voltages to identify the supply voltages that are present. The PMIC may be configured with a power-up initialization mode of operation through an EFUSE/MTP register, including a first bit to control power up of a voltage regulator of the PMIC with the main supply voltage or the backup supply voltage. Another bit may control power up of the voltage regulator with the backup supply voltage in the dual-supply or the single-supply configuration. The PMIC may execute one of four power-up sequences based on the monitored status of the supply voltages and the configured power-up initialization mode of operation.

公开(公告)号：US20220358989A1

公开(公告)日：2022-11-10

申请号：US17725026

申请日：2022-04-20

Applicant: Rambus Inc.

Inventor： Panduka Wijetunga ,  Aws Shallal ,  Joey M. Esteves

IPC: G11C11/4074

Abstract: A power-management integrated circuit (PMIC) is installed on a memory module to optimize power use among a collection of memory devices. The PMIC includes external power-supply nodes that receive relatively high and low supply voltages. Depending on availability, the PMIC uses one or both of these supply voltages to generate a managed supply voltage for powering the memory devices. The PMIC selects between operational modes for improved efficiency in dependence upon the availability of one or both externally provided supply voltages.

公开(公告)号：US20220208267A1

公开(公告)日：2022-06-30

申请号：US17573456

申请日：2022-01-11

Applicant: Rambus Inc.

Inventor： Aws Shallal ,  Nigel Alvares ,  Sarvagya Kochak

IPC: G11C14/00 ,  G06F12/0804

Abstract: A system that includes a non-volatile memory subsystem having non-volatile memory. The system also includes a plurality of memory modules that are separate from the non-volatile memory subsystem. Each memory module can include a plurality of random access memory packages where each first random access memory package includes a primary data port and a backup data port. Each memory module can include a storage interface circuit coupled to the backup data ports of the random access memory packages. The storage interface circuit offloads data from the memory module in the event of a power loss by receiving data from the backup data ports of the random access memory packages and transmitting the data to the non-volatile memory subsystem.

公开(公告)号：US20210343318A1

公开(公告)日：2021-11-04

申请号：US17284433

申请日：2019-10-07

Applicant: Rambus Inc.

Inventor： Aws Shallal ,  Larry Grant Giddens

IPC: G11C7/10 ,  G11C7/22 ,  G11C11/4093

Abstract: A buffer chip includes a first set of input/output (I/O) pins a second set of I/O pins, and is configurable to operate in one of a first mode or a second mode. The first set of I/O pins and the second set of I/O pins are configured to convey first signals between the buffer chip and one or more volatile memory devices on a memory module when the buffer chip is configured to operate in the first mode. The first set of I/O pins is configured to convey the first signals between the buffer chip and the one or more volatile memory devices and the second set of I/O pins is configured to convey second signals between more non-volatile memory devices on the memory module when the buffer chip is configured to operate in the second mode.

公开(公告)号：US20210311888A1

公开(公告)日：2021-10-07

申请号：US17306410

申请日：2021-05-03

Applicant: Rambus Inc.

Inventor： Aws Shallal ,  Larry Grant Giddens

IPC: G06F13/16 ,  G06F13/42

Abstract: A memory module includes a plurality of memory integrated circuit (IC) packages to store data and a command buffer IC to buffer one or more memory commands destined for the memory IC packages. The command buffer IC includes a first interface circuit and one or more second interface circuits. The first interface circuit receives the one or more memory commands The one or more second interface circuits output a pre-programmed command sequence to one or more devices separate from the command buffer IC, the pre-programmed command sequence output in response to the one or more memory commands matching a pre-programmed reference command pattern.