公开(公告)号：US20250047469A1

公开(公告)日：2025-02-06

申请号：US18669731

申请日：2024-05-21

Applicant: Rambus Inc.

Inventor： Evan Lawrence Erickson ,  Michael Alexander Hamburg ,  Taeksang Song ,  Wendy Elsasser

IPC: H04L9/06 ,  G06F21/60

Abstract: Techniques for providing reduced latency metadata encryption and decryption are described herein. A memory buffer device having a cryptographic circuit to receive a first data and a first metadata associated with the first data. The cryptographic circuit can encrypt or decrypt the first metadata using a first cryptographic algorithm. The cryptographic circuit can encrypt or decrypt the first data using a second cryptographic algorithm. The first data and the first metadata can be stored at a same location, within a memory device, corresponding to a memory address.

公开(公告)号：US20240428840A1

公开(公告)日：2024-12-26

申请号：US18750027

申请日：2024-06-21

Applicant: Rambus Inc.

Inventor： Taeksang Song ,  Thomas Vogelsang

IPC: G11C11/406

Abstract: An integrated circuit (IC) memory device includes an array of storage cells configured into multiple regions. Monitoring circuitry is coupled to each of the multiple regions to detect and generate per-region operating parameter information. Refresh circuitry generates per-region refresh information for the multiple regions based on the per-region operating parameter information.

公开(公告)号：US20240427661A1

公开(公告)日：2024-12-26

申请号：US18707281

申请日：2022-11-14

Applicant: Rambus Inc.

Inventor： Taeksang Song

IPC: G06F11/10 ,  G06F11/14

Abstract: Technologies for storing burst error information in a buffer structure and signaling to prevent overflow and over-writing the buffer structure are described. One controller device includes error detection logic, a buffer, and buffer control logic. The error detection logic detects an error in a read operation associated with a memory device coupled to the controller device. The buffer stores error information associated with the error. The buffer control logic generates and outputs a first signal responsive to the buffer being full.

公开(公告)号：US20230177176A1

公开(公告)日：2023-06-08

申请号：US18074225

申请日：2022-12-02

Applicant: Rambus Inc.

Inventor： Evan Lawrence Erickson ,  Taeksang Song

IPC: G06F21/60 ,  G06F21/85 ,  G06F21/54

CPC classification number: G06F21/602 ,  G06F21/85 ,  G06F21/54

Abstract: A multi-processor device is disclosed. The multi-processor device includes memory interface circuitry to access external memory. A primary processor is selectively coupled to the interface circuitry. A secure processor enables/disables access to the memory interface circuitry by the primary processor based on an operating mode of the multi-processor IC chip.