公开(公告)号：US20250047469A1

公开(公告)日：2025-02-06

申请号：US18669731

申请日：2024-05-21

Applicant: Rambus Inc.

Inventor： Evan Lawrence Erickson ,  Michael Alexander Hamburg ,  Taeksang Song ,  Wendy Elsasser

IPC: H04L9/06 ,  G06F21/60

Abstract: Techniques for providing reduced latency metadata encryption and decryption are described herein. A memory buffer device having a cryptographic circuit to receive a first data and a first metadata associated with the first data. The cryptographic circuit can encrypt or decrypt the first metadata using a first cryptographic algorithm. The cryptographic circuit can encrypt or decrypt the first data using a second cryptographic algorithm. The first data and the first metadata can be stored at a same location, within a memory device, corresponding to a memory address.

公开(公告)号：US20240146336A1

公开(公告)日：2024-05-02

申请号：US18498832

申请日：2023-10-31

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Michael Alexander Hamburg ,  John Eric Linstadt ,  Evan Lawrence Erickson

IPC: H03M13/00 ,  H03M13/15 ,  H03M13/43

CPC classification number: H03M13/6312 ,  H03M13/159 ,  H03M13/43

Abstract: Aspects and implementations include systems and techniques that detect and correct failure of data storage and communication operations, including obtaining a first plurality of values, selecting a first plurality of error correction values to generate a first codeword, wherein the first codeword is associated with a plurality of syndrome values that encode a second subset of the first plurality of values, and causing a first processing device or a second processing device to restore the first plurality of values based on the first codeword.

公开(公告)号：US20230177176A1

公开(公告)日：2023-06-08

申请号：US18074225

申请日：2022-12-02

Applicant: Rambus Inc.

Inventor： Evan Lawrence Erickson ,  Taeksang Song

IPC: G06F21/60 ,  G06F21/85 ,  G06F21/54

CPC classification number: G06F21/602 ,  G06F21/85 ,  G06F21/54

Abstract: A multi-processor device is disclosed. The multi-processor device includes memory interface circuitry to access external memory. A primary processor is selectively coupled to the interface circuitry. A secure processor enables/disables access to the memory interface circuitry by the primary processor based on an operating mode of the multi-processor IC chip.

公开(公告)号：US20250110670A1

公开(公告)日：2025-04-03

申请号：US18887285

申请日：2024-09-17

Applicant: Rambus Inc.

Inventor： Evan Lawrence Erickson

IPC: G06F3/06

Abstract: A memory system enables a host device to flexibly allocate compressed storage managed by a memory buffer device. The host device allocates a first block of host-visible addresses associated with the compressed region and a memory buffer device allocates a corresponding second block of host-visible memory. The host device may migrate uncompressed data to and from compressed storage by referencing an address in the second block (with compression and decompression managed by the memory buffer device) and may migrate compressed data to and from compressed storage (bypassing compression and decompression on the memory buffer device) by instead referencing an address in the first block.

公开(公告)号：US12204446B2

公开(公告)日：2025-01-21

申请号：US18140441

申请日：2023-04-27

Applicant: Rambus Inc.

Inventor： Evan Lawrence Erickson ,  Christopher Haywood

IPC: G06F12/02 ,  G06F12/0891

Abstract: A buffer/interface device of a memory node reads a block of data (e.g., page). As each unit of data (e.g., cache line sized) of the block is read, it is compared against one or more predefined patterns (e.g., all 0's, all 1's, etc.). If the block (page) is only storing one of the predefined patterns, a flag in the page table entry for the block is set to indicate the block is only storing one of the predefined patterns. The physical memory the block was occupying may then be deallocated so other data may be stored using those physical memory addresses.

公开(公告)号：US12147351B2

公开(公告)日：2024-11-19

申请号：US18139220

申请日：2023-04-25

Applicant: Rambus Inc.

Inventor： Evan Lawrence Erickson ,  Christopher Haywood ,  Mark D. Kellam

IPC: G06F12/10 ,  G06F12/0804 ,  G06F12/0882 ,  G06F12/1009 ,  G06F12/123 ,  G06F13/16

Abstract: Memory pages are background-relocated from a low-latency local operating memory of a server computer to a higher-latency memory installation that enables high-resolution access monitoring and thus access-demand differentiation among the relocated memory pages. Higher access-demand memory pages are background-restored to the low-latency operating memory, while lower access-demand pages are maintained in the higher latency memory installation and yet-lower access-demand pages are optionally moved to yet higher-latency memory installation.

公开(公告)号：US20240119001A1

公开(公告)日：2024-04-11

申请号：US18377597

申请日：2023-10-06

Applicant: Rambus Inc.

Inventor： Taeksang Song ,  Christopher Haywood ,  Evan Lawrence Erickson

IPC: G06F12/0802

CPC classification number: G06F12/0802

Abstract: Disclosed are techniques for storing data decompressed from the compressed pages of a memory block when servicing data access request from a host device of a memory system to the compressed page data in which the memory block has been compressed into multiple compressed pages. A cache buffer may store the decompressed data for a few compressed pages to save decompression memory space. The memory system may keep track of the number of accesses to the decompressed data in the cache and the number of compressed pages that have been decompressed into the cache to calculate a metric associated with the frequency of access to the compressed pages within the memory block. If the metric does not exceed a threshold, additional compressed pages are decompressed into the cache. Otherwise, all the compressed pages within the memory block are decompressed into a separately allocated memory space to reduce data access latency.

公开(公告)号：US20230376412A1

公开(公告)日：2023-11-23

申请号：US18030971

申请日：2021-10-11

Applicant: RAMBUS INC.

Inventor： Evan Lawrence Erickson ,  Christopher Haywood

IPC: G06F12/02

CPC classification number: G06F12/0292 ,  G06F12/023 ,  G06F2212/154

Abstract: An integrated circuit device includes a first memory to support address translation between local addresses and fabric addresses and a processing circuit, operatively coupled to the first memory. The processing circuit allocates, on a dynamic basis as a donor, a portion of first local memory of a local server as first far memory for access for a first remote server, or as a requester receives allocation of second far memory from the first remote server or a second remote server for access by the local server. The processing circuit bridges the access by the first remote server to the allocated portion of first local memory as the first far memory, through the fabric addresses and the address translation supported by the first memory, or bridge the access by the local server to the second far memory, through the address translation supported by the first memory, and the fabric addresses.

公开(公告)号：US20230161599A1

公开(公告)日：2023-05-25

申请号：US17968488

申请日：2022-10-18

Applicant: Rambus Inc.

Inventor： Evan Lawrence Erickson

IPC: G06F9/4401 ,  H04L67/141

CPC classification number: G06F9/4406 ,  H04L67/141

Abstract: A device includes interface circuitry to receive requests from at least one host system, a primary processor coupled to the interface circuitry, and a secure processor coupled to the primary processor. In response to a failure of the primary processor, the secure processor is to: verify a log retrieval command received via the interface circuitry, wherein the log retrieval command is cryptographically signed; in response to the verification, retrieve crash dump data stored in memory that is accessible by the primary processor; generate a log file that comprises the retrieved crash dump data; and cause the log file to be transmitted to the at least one host system over a sideband link that is coupled externally to the interface circuitry.

公开(公告)号：US20250110917A1

公开(公告)日：2025-04-03

申请号：US18919053

申请日：2024-10-17

Applicant: Rambus Inc.

Inventor： Michael Raymond Miller ,  Evan Lawrence Erickson

IPC: G06F15/78 ,  G06F21/72

Abstract: A multi-processor device is disclosed. The multi-processor device includes interface circuitry to receive requests from at least one host device. A primary processor is coupled to the interface circuitry to process the requests in the absence of a failure event associated with the primary processor. A secondary processor processes operations on behalf of the primary processor and selectively receives the requests from the interface circuitry based on detection of the failure event associated with the primary processor.