公开(公告)号：US20110222552A1

公开(公告)日：2011-09-15

申请号：US12974477

申请日：2010-12-21

申请人： Deepak Mital ,  James Clee ,  Jerry Pirog

发明人： Deepak Mital ,  James Clee ,  Jerry Pirog

IPC分类号： H04L12/56

CPC分类号： G06F15/167 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/4881 ,  H04L47/522

摘要： Described embodiments provide a packet classifier for a network processor that generates tasks corresponding to each received packet. The packet classifier includes a scheduler to generate contexts corresponding to tasks received by the packet classifier from a plurality of processing modules of the network processor. A multi-thread instruction engine processes threads of instructions, each thread of instructions corresponding to a context received from the scheduler. A thread status manager maintains a thread status table having N entries to track up to N active threads. Each status entry includes a valid status indicator, a sequence value, and a thread indicator. A sequence counter generates a sequence value for each thread and is incremented when processing of a thread is started, and is decremented when a thread is completed, by the multi-thread instruction engine. Instructions are processed by the multi-thread instruction engine in the order in which the threads were started.

摘要翻译： 描述的实施例提供了一种用于生成与每个接收的分组相对应的任务的网络处理器的分组分类器。 分组分类器包括调度器，用于从网络处理器的多个处理模块生成与分组分类器接收到的任务相对应的上下文。 多线程指令引擎处理指令的线程，每个指令线程与从调度器接收的上下文相对应。 线程状态管理器维护具有N个条目的线程状态表以跟踪多达N个活动线程。 每个状态条目包括有效的状态指示符，序列值和线程指示符。 序列计数器产生每个线程的序列值，并且当线程的处理开始时递增，并且在线程完成时由多线程指令引擎递减。 指令由多线程指令引擎以线程启动的顺序进行处理。

公开(公告)号：US20110222540A1

公开(公告)日：2011-09-15

申请号：US12971742

申请日：2010-12-17

申请人： Deepak Mital ,  James Clee ,  Jerry Pirog

发明人： Deepak Mital ,  James Clee ,  Jerry Pirog

IPC分类号： H04L12/56

CPC分类号： G06F15/167 ,  G06F9/3851 ,  G06F9/3885

摘要： Described embodiments provide a packet assembler for a network processor. The network processor includes a plurality of processing modules for processing received packets into one or more processed-packet portions. A shared system memory of the network processor receives processed-packet portions corresponding to packet assemblies. Each of the packet assemblies has associated tasks. A packet assembly processor constructs an output packet for each packet assembly from the processed-packet portions in accordance with instructions from the tasks associated with the packet assembly. The packet assembly processor coordinates storage of the processed-packet portions for each output packet that is read from the system memory based on the instructions from the tasks associated with the corresponding packet assembly.

摘要翻译： 所描述的实施例提供了一种用于网络处理器的分组组装器。 网络处理器包括用于将接收到的分组处理成一个或多个处理分组部分的多个处理模块。 网络处理器的共享系统存储器接收对应于分组组件的处理分组部分。 每个分组组件都具有相关联的任务。 分组组合处理器根据来自与分组组合相关联的任务的指令，从处理分组部分为每个分组组合构建输出分组。 分组组合处理器基于来自与相应分组组合相关联的任务的指令来协调从系统存储器读取的每个输出分组的处理分组部分的存储。