公开(公告)号：US20170286337A1

公开(公告)日：2017-10-05

申请号：US15087154

申请日：2016-03-31

Applicant: Ren Wang ,  Yipeng Wang ,  Jr-Shian Tsai ,  Andrew Herdrich ,  Tsung-Yuan Tai ,  Niall McDonnell ,  Stephen Van Doren ,  David Sonnier ,  Debra Bernstein ,  Hugh Wilkinson ,  Narender Vangati ,  Stephen Miller ,  Gage Eads ,  Andrew Cunningham ,  Jonathan Kenny ,  Bruce Richardson ,  William Burroughs ,  Joseph Hasting ,  An Yan ,  James Clee ,  Te Ma ,  Jerry Pirog ,  Jamison Whitesell

Inventor： Ren Wang ,  Yipeng Wang ,  Jr-Shian Tsai ,  Andrew Herdrich ,  Tsung-Yuan Tai ,  Niall McDonnell ,  Stephen Van Doren ,  David Sonnier ,  Debra Bernstein ,  Hugh Wilkinson ,  Narender Vangati ,  Stephen Miller ,  Gage Eads ,  Andrew Cunningham ,  Jonathan Kenny ,  Bruce Richardson ,  William Burroughs ,  Joseph Hasting ,  An Yan ,  James Clee ,  Te Ma ,  Jerry Pirog ,  Jamison Whitesell

IPC: G06F13/36 ,  G06F13/40 ,  G06F12/10 ,  G06F13/24

CPC classification number: G06F13/36 ,  G06F12/1027 ,  G06F13/24 ,  G06F13/4004 ,  G06F2212/1021 ,  G06F2212/50 ,  G06F2212/68

Abstract: Technologies for a distributed hardware queue manager include a compute device having a procesor. The processor includes two or more hardware queue managers as well as two or more processor cores. Each processor core can enqueue or dequeue data from the hardware queue manager. Each hardware queue manager can be configured to contain several queue data structures. In some embodiments, the queues are addressed by the processor cores using virtual queue addresses, which are translated into physical queue addresses for accessing the corresponding hardware queue manager. The virtual queues can be moved from one physical queue in one hardware queue manager to a different physical queue in a different physical queue manager without changing the virtual address of the virtual queue.

公开(公告)号：US20200004584A1

公开(公告)日：2020-01-02

申请号：US16021471

申请日：2018-06-28

Applicant: William Burroughs ,  James Clee ,  Ambalavanar Arulambalam ,  Joseph Hasting ,  Niall Mcdonnell

Inventor： William Burroughs ,  James Clee ,  Ambalavanar Arulambalam ,  Joseph Hasting ,  Niall Mcdonnell

IPC: G06F9/48

Abstract: In an embodiment, a processor for queue selection includes a plurality of processing engines (PEs) to execute threads, and a hardware queue manager. The hardware queue manager is to: detect that a first class lacks valid requests to be scheduled, the first class comprising a first plurality of scheduling queues, the first class associated with a first credit count; select a second class based on a second credit count associated with the second class, the second class comprising a second plurality of scheduling queues; and in response to a selection of the second class based on the second credit count, select a queue in the selected second class. Other embodiments are described and claimed.

公开(公告)号：US08514874B2

公开(公告)日：2013-08-20

申请号：US12975880

申请日：2010-12-22

Applicant: Deepak Mital ,  James Clee

Inventor： Deepak Mital ,  James Clee

IPC: H04L12/56

CPC classification number: G06F15/167 ,  G06F9/3851 ,  G06F9/3885 ,  H04L47/2441

Abstract: Described embodiments provide a packet classifier for a network processor that generates tasks corresponding to each received packet. The packet classifier includes a scheduler to generate a thread of contexts for each task received by the packet classifier from a plurality of processing modules of the network processor. The scheduler includes one or more output queues to temporarily store contexts. Each thread corresponds to an order of instructions applied to the corresponding packet, and includes an identifier of a corresponding one of the output queues. The scheduler sends the contexts to a multi-thread instruction engine that processes the threads. An arbiter selects one of the output queues in order to provide output packets to the multi-thread instruction engine, the output packets associated with a corresponding thread of contexts. Each output queue transmits output packets corresponding to a given thread contiguously in the order in which the threads started.

Abstract translation: 描述的实施例提供了一种用于生成与每个接收的分组相对应的任务的网络处理器的分组分类器。 分组分类器包括调度器，用于从网络处理器的多个处理模块生成由分组分类器接收的每个任务的上下文线程。 调度器包括用于临时存储上下文的一个或多个输出队列。 每个线程对应于应用于相应分组的指令的顺序，并且包括输出队列中相应的一个的标识符。 调度器将上下文发送到处理线程的多线程指令引擎。 仲裁器选择一个输出队列，以向多线程指令引擎提供输出分组，输出分组与相应的上下文线程相关联。 每个输出队列按照线程开始的顺序连续传送与给定线程相对应的输出数据包。

公开(公告)号：US20110222553A1

公开(公告)日：2011-09-15

申请号：US12975880

申请日：2010-12-22

Applicant: Deepak Mital ,  James Clee

Inventor： Deepak Mital ,  James Clee

IPC: H04L12/56

CPC classification number: G06F15/167 ,  G06F9/3851 ,  G06F9/3885 ,  H04L47/2441

Abstract: Described embodiments provide a packet classifier for a network processor that generates tasks corresponding to each received packet. The packet classifier includes a scheduler to generate a thread of contexts for each task received by the packet classifier from a plurality of processing modules of the network processor. The scheduler includes one or more output queues to temporarily store contexts. Each thread corresponds to an order of instructions applied to the corresponding packet, and includes an identifier of a corresponding one of the output queues. The scheduler sends the contexts to a multi-thread instruction engine that processes the threads. An arbiter selects one of the output queues in order to provide output packets to the multi-thread instruction engine, the output packets associated with a corresponding thread of contexts. Each output queue transmits output packets corresponding to a given thread contiguously in the order in which the threads started.

Abstract translation: 描述的实施例提供了一种用于生成与每个接收的分组相对应的任务的网络处理器的分组分类器。 分组分类器包括调度器，用于从网络处理器的多个处理模块生成由分组分类器接收的每个任务的上下文线程。 调度器包括用于临时存储上下文的一个或多个输出队列。 每个线程对应于应用于相应分组的指令的顺序，并且包括输出队列中相应的一个的标识符。 调度器将上下文发送到处理线程的多线程指令引擎。 仲裁器选择一个输出队列，以向多线程指令引擎提供输出分组，输出分组与相应的上下文线程相关联。 每个输出队列按照线程开始的顺序连续传送与给定线程相对应的输出数据包。

公开(公告)号：US08943507B2

公开(公告)日：2015-01-27

申请号：US12971742

申请日：2010-12-17

Applicant: Deepak Mital ,  James Clee ,  Jerry Pirog

Inventor： Deepak Mital ,  James Clee ,  Jerry Pirog

IPC: G06F7/68 ,  G06F15/167 ,  G06F9/38

CPC classification number: G06F15/167 ,  G06F9/3851 ,  G06F9/3885

Abstract: Described embodiments provide a packet assembler for a network processor. The network processor includes a plurality of processing modules for processing received packets into one or more processed-packet portions. A shared system memory of the network processor receives processed-packet portions corresponding to packet assemblies. Each of the packet assemblies has associated tasks. A packet assembly processor constructs an output packet for each packet assembly from the processed-packet portions in accordance with instructions from the tasks associated with the packet assembly. The packet assembly processor coordinates storage of the processed-packet portions for each output packet that is read from the system memory based on the instructions from the tasks associated with the corresponding packet assembly.

Abstract translation: 所描述的实施例提供了一种用于网络处理器的分组组装器。 网络处理器包括用于将接收到的分组处理成一个或多个处理分组部分的多个处理模块。 网络处理器的共享系统存储器接收对应于分组组件的处理分组部分。 每个分组组件都具有相关联的任务。 分组组合处理器根据来自与分组组合相关联的任务的指令，从处理分组部分为每个分组组合构建输出分组。 分组组合处理器基于来自与相应分组组合相关联的任务的指令来协调从系统存储器读取的每个输出分组的处理分组部分的存储。

公开(公告)号：US20110222552A1

公开(公告)日：2011-09-15

申请号：US12974477

申请日：2010-12-21

Applicant: Deepak Mital ,  James Clee ,  Jerry Pirog

Inventor： Deepak Mital ,  James Clee ,  Jerry Pirog

IPC: H04L12/56

CPC classification number: G06F15/167 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/4881 ,  H04L47/522

Abstract: Described embodiments provide a packet classifier for a network processor that generates tasks corresponding to each received packet. The packet classifier includes a scheduler to generate contexts corresponding to tasks received by the packet classifier from a plurality of processing modules of the network processor. A multi-thread instruction engine processes threads of instructions, each thread of instructions corresponding to a context received from the scheduler. A thread status manager maintains a thread status table having N entries to track up to N active threads. Each status entry includes a valid status indicator, a sequence value, and a thread indicator. A sequence counter generates a sequence value for each thread and is incremented when processing of a thread is started, and is decremented when a thread is completed, by the multi-thread instruction engine. Instructions are processed by the multi-thread instruction engine in the order in which the threads were started.

Abstract translation: 描述的实施例提供了一种用于生成与每个接收的分组相对应的任务的网络处理器的分组分类器。 分组分类器包括调度器，用于从网络处理器的多个处理模块生成与分组分类器接收到的任务相对应的上下文。 多线程指令引擎处理指令的线程，每个指令线程与从调度器接收的上下文相对应。 线程状态管理器维护具有N个条目的线程状态表以跟踪多达N个活动线程。 每个状态条目包括有效的状态指示符，序列值和线程指示符。 序列计数器产生每个线程的序列值，并且当线程的处理开始时递增，并且在线程完成时由多线程指令引擎递减。 指令由多线程指令引擎以线程启动的顺序进行处理。

公开(公告)号：US20110222540A1

公开(公告)日：2011-09-15

申请号：US12971742

申请日：2010-12-17

Applicant: Deepak Mital ,  James Clee ,  Jerry Pirog

Inventor： Deepak Mital ,  James Clee ,  Jerry Pirog

IPC: H04L12/56

CPC classification number: G06F15/167 ,  G06F9/3851 ,  G06F9/3885

Abstract: Described embodiments provide a packet assembler for a network processor. The network processor includes a plurality of processing modules for processing received packets into one or more processed-packet portions. A shared system memory of the network processor receives processed-packet portions corresponding to packet assemblies. Each of the packet assemblies has associated tasks. A packet assembly processor constructs an output packet for each packet assembly from the processed-packet portions in accordance with instructions from the tasks associated with the packet assembly. The packet assembly processor coordinates storage of the processed-packet portions for each output packet that is read from the system memory based on the instructions from the tasks associated with the corresponding packet assembly.

Abstract translation: 所描述的实施例提供了一种用于网络处理器的分组组装器。 网络处理器包括用于将接收到的分组处理成一个或多个处理分组部分的多个处理模块。 网络处理器的共享系统存储器接收对应于分组组件的处理分组部分。 每个分组组件都具有相关联的任务。 分组组合处理器根据来自与分组组合相关联的任务的指令，从处理分组部分为每个分组组合构建输出分组。 分组组合处理器基于来自与相应分组组合相关联的任务的指令来协调从系统存储器读取的每个输出分组的处理分组部分的存储。

公开(公告)号：US08910171B2

公开(公告)日：2014-12-09

申请号：US12974477

申请日：2010-12-21

Applicant: Deepak Mital ,  James Clee ,  Jerry Pirog

Inventor： Deepak Mital ,  James Clee ,  Jerry Pirog

IPC: G06F9/52 ,  G06F15/167 ,  G06F9/38 ,  G06F9/48 ,  H04L12/873

CPC classification number: G06F15/167 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/4881 ,  H04L47/522

Abstract: Described embodiments provide a packet classifier for a network processor that generates tasks corresponding to each received packet. The packet classifier includes a scheduler to generate contexts corresponding to tasks received by the packet classifier from a plurality of processing modules of the network processor. A multi-thread instruction engine processes threads of instructions, each thread of instructions corresponding to a context received from the scheduler. A thread status manager maintains a thread status table having N entries to track up to N active threads. Each status entry includes a valid status indicator, a sequence value, and a thread indicator. A sequence counter generates a sequence value for each thread and is incremented when processing of a thread is started, and is decremented when a thread is completed, by the multi-thread instruction engine. Instructions are processed by the multi-thread instruction engine in the order in which the threads were started.

Abstract translation: 描述的实施例提供了一种用于生成与每个接收的分组相对应的任务的网络处理器的分组分类器。 分组分类器包括调度器，用于从网络处理器的多个处理模块生成与分组分类器接收到的任务相对应的上下文。 多线程指令引擎处理指令的线程，每个指令线程与从调度器接收的上下文相对应。 线程状态管理器维护具有N个条目的线程状态表以跟踪多达N个活动线程。 每个状态条目包括有效的状态指示符，序列值和线程指示符。 序列计数器产生每个线程的序列值，并且当线程的处理开始时递增，并且在线程完成时由多线程指令引擎递减。 指令由多线程指令引擎以线程启动的顺序进行处理。