公开(公告)号：US20130212362A1

公开(公告)日：2013-08-15

申请号：US13839278

申请日：2013-03-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshitaka TAKAHASHI ,  Shoji MURAMATSU ,  Tetsuaki NAKAMIKAWA ,  Hiroyuki HAMASAKI ,  So OTSUKA

IPC: G06F9/30

CPC classification number: G06F9/3001 ,  G06F9/30101 ,  G06T1/00

Abstract: A restriction is given to the calculation function for image processing achieved by the hard-wired system and the memory access control of a buffer memory, and a range of the restriction is made variable by a program control and others. Data is inputted to the buffer memory from the outside with a restriction of “in units of memory line”, and the number of memory lines and positions of the same to which data is inputted can be programmable by the control circuit. The arithmetic circuit is subjected to the restriction of performing the calculation in units of data of one or plural memory lines supplied from the buffer memory, and a calculation processing content in units of calculation processing for the units of data can be programmably assigned by the control circuit.

Abstract translation: 对由硬接线系统和缓冲存储器的存储器访问控制实现的图像处理的计算功能进行限制，并且通过程序控制等来限制范围变化。 数据以“以存储线为单位”的限制从外部输入到缓冲存储器，并且通过控制电路可编程输入数据的存储器线数和位置数。 算术电路受到以缓冲存储器提供的一个或多个存储器线的数据为单位执行计算的限制，并且可以通过控制来可编程地分配用于数据单元的计算处理单位的计算处理内容 电路。