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11.发明授权Method for producing a metal-gate MOS transistor, in particular a PMOS transistor, and corresponding integrated circuit 有权用于制造金属栅极MOS晶体管，特别是PMOS晶体管的方法和相应的集成电路公开(公告)号：US09257518B2
公开(公告)日：2016-02-09
申请号：US14254994
申请日：2014-04-17
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Sylvain Baudot , Pierre Caubet , Florian Domengie
IPC: H01L21/00 , H01L29/423 , H01L27/088 , H01L21/8234 , H01L21/28 , H01L29/49 , H01L29/78
CPC classification number: H01L29/42372 , H01L21/28079 , H01L21/28088 , H01L21/8234 , H01L27/088 , H01L29/4966 , H01L29/78
Abstract: At least one MOS transistor is produced by forming a dielectric region above a substrate and forming a gate over the dielectric region. The gate is formed to include a metal gate region. Formation of the metal gate region includes: forming a layer of a first material configured to reduce an absolute value of a threshold voltage of the transistor, and configuring a part of the metal gate region so as also to form a diffusion barrier above the layer of the first material. Then, doped source and drain regions are formed using a dopant activation anneal.
Abstract translation: 至少一个MOS晶体管是通过在衬底上形成电介质区域并在电介质区域上形成栅极来制造的。 栅极形成为包括金属栅极区域。 金属栅极区域的形成包括：形成第一材料层，其被配置为降低晶体管的阈值电压的绝对值，并且构成金属栅极区域的一部分，以便在层的上方形成扩散阻挡层 第一种材料。 然后，使用掺杂剂激活退火形成掺杂源极和漏极区。
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12.发明申请METHOD FOR PRODUCING A METAL-GATE MOS TRANSISTOR, IN PARTICULAR A PMOS TRANSISTOR, AND CORRESPONDING INTEGRATED CIRCUIT 有权用于生产金属栅极MOS晶体管，特别是PMOS晶体管和相应的集成电路的方法公开(公告)号：US20140319616A1
公开(公告)日：2014-10-30
申请号：US14254994
申请日：2014-04-17
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Sylvain Baudot , Pierre Caubet , Florian Domengie
IPC: H01L29/423 , H01L21/8234 , H01L27/088
CPC classification number: H01L29/42372 , H01L21/28079 , H01L21/28088 , H01L21/8234 , H01L27/088 , H01L29/4966 , H01L29/78
Abstract: At least one MOS transistor is produced by forming a dielectric region above a substrate and forming a gate over the dielectric region. The gate is formed to include a metal gate region. Formation of the metal gate region includes: forming a layer of a first material configured to reduce an absolute value of a threshold voltage of the transistor, and configuring a part of the metal gate region so as also to form a diffusion barrier above the layer of the first material. Then, doped source and drain regions are formed using a dopant activation anneal.
Abstract translation: 至少一个MOS晶体管是通过在衬底上形成电介质区域并在电介质区域上形成栅极来制造的。 栅极形成为包括金属栅极区域。 金属栅极区域的形成包括：形成第一材料层，其被配置为降低晶体管的阈值电压的绝对值，并且构成金属栅极区域的一部分，以便在层的上方形成扩散阻挡层 第一种材料。 然后，使用掺杂剂激活退火形成掺杂源极和漏极区。
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