公开(公告)号：US09390786B2

公开(公告)日：2016-07-12

申请号：US14813278

申请日：2015-07-30

Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.

Inventor： Christophe Lecocq ,  Kaya Can Akyel ,  Amit Chhabra ,  Dibya Dipti

IPC: G11C11/34 ,  G11C11/417 ,  G11C11/412 ,  H01L27/11

CPC classification number: G11C11/417 ,  G11C11/412 ,  H01L27/1104

Abstract: An SRAM cell is formed of FDSOI-type NMOS and PMOS transistors. A doped well extends under the NMOS and PMOS transistors and is separated therefrom by an insulating layer. A bias voltage is applied to the doped well. The applied bias voltage is adjusted according to a state of the memory cell. For example, a temperature of the memory cell is sensed and the bias voltage adjusted as a function of the sensed temperature. The adjustment in the bias voltage is configured so that threshold voltages of the NMOS and PMOS transistors are substantially equal to n and p target threshold voltages, respectively.

Abstract translation: SRAM单元由FDSOI型NMOS和PMOS晶体管形成。 掺杂阱在NMOS和PMOS晶体管的下方延伸，并通过绝缘层与其分离。 偏置电压施加到掺杂阱。 施加的偏置电压根据存储单元的状态进行调整。 例如，感测存储器单元的温度，并根据检测到的温度调整偏置电压。 偏置电压的调整被配置为使得NMOS和PMOS晶体管的阈值电压分别基本上等于n和p个目标阈值电压。