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    SEMICONDUCTOR STORAGE DEVICE
    1.
    发明公开
    SEMICONDUCTOR STORAGE DEVICE 审中-公开

    公开(公告)号：US20240341074A1

    公开(公告)日：2024-10-10

    申请号：US18749271

    申请日：2024-06-20

    Applicant: Socionext Inc.

    Inventor： Masanobu HIROSE ,  Yasunori MURASE

    IPC: H10B10/00 ,  G11C11/412 ,  G11C11/419

    CPC classification number: H10B10/12 ,  G11C11/412 ,  G11C11/419 ,  H10B10/18

    Abstract: Nanosheets 21 to 23 are formed in line in this order in the X direction, and nanosheets 24 to 26 are formed in line in this order in the X direction. In a buried interconnect layer, a power line 11 is formed between the nanosheets 22 and 25 as viewed in plan. A face of the nanosheet 22 on a first side as one of the sides in the X direction is exposed from a gate interconnect 32. A face of the nanosheet 25 on a second side as the other side in the X direction is exposed from a gate interconnect 35.

    Three-port SRAM cell and layout method
    3.
    发明授权
    Three-port SRAM cell and layout method 有权

    公开(公告)号：US12114473B2

    公开(公告)日：2024-10-08

    申请号：US17828123

    申请日：2022-05-31

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Jhon-Jhy Liaw

    IPC: G11C7/12 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419 ,  H10B10/00 ,  G11C8/08 ,  G11C8/16

    CPC classification number: H10B10/18 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419 ,  G11C7/12 ,  G11C8/08 ,  G11C8/16

    Abstract: Semiconductor devices are provided. A write port circuit is configured to perform a write function according to the write word line and the first and second write bit lines. The first read port circuit is configured to perform first read function according to the first read bit line and the first read word line. The second read port circuit is configured to perform second read function according to the second read bit line and the second read word line. The transistors of the first and second read port circuits share a first active structure extending in the first direction. The first read bit line and the second read bit line extend in the first direction in a first metallization layer, and the first write bit line and the second write bit line extend in the first direction in a second metallization layer over the first metallization layer.

    OPERATION SCHEME FOR FOUR TRANSISTOR STATIC RANDOM ACCESS MEMORY
    7.
    发明公开
    OPERATION SCHEME FOR FOUR TRANSISTOR STATIC RANDOM ACCESS MEMORY 审中-公开

    公开(公告)号：US20240296883A1

    公开(公告)日：2024-09-05

    申请号：US18418060

    申请日：2024-01-19

    Applicant: FlashSilicon Incorporation

    Inventor： LEE WANG

    IPC: G11C11/419 ,  G11C11/412 ,  G11C11/418

    CPC classification number: G11C11/419 ,  G11C11/412 ,  G11C11/418

    Abstract: A memory device is disclosed, comprising a 4T-SRAM cell and a read circuit. The 4T-SRAM cell comprising two P-type MOSFET devices for a data bit storage and two N-type MOSFET for accessing switches has benefits of less numbers of MOSFET devices for smaller cell size and low leakage current than the conventional 6T-SRAM cell. The read circuit comprises a latch and a discharge device. The latch with two output nodes is coupled between a supply voltage rail and a ground voltage rail. The discharge device is coupled to the two output nodes, a bit line pair and the ground voltage rail. Since one of two storage nodes for the 4T-SRAM cell is floating, the stored data in the 4T-SRAM cell is vulnerable for conventional read operations. The read circuit of the invention resolves the vulnerability issue of the 4T-SRAM cell.

    Low power and fast memory reset
    9.
    发明授权
    Low power and fast memory reset 有权

    公开(公告)号：US12068026B2

    公开(公告)日：2024-08-20

    申请号：US17852677

    申请日：2022-06-29

    Applicant: STMicroelectronics International N.V.

    Inventor： Harsh Rawat ,  Praveen Kumar Verma

    IPC: G11C11/419 ,  G11C11/412

    CPC classification number: G11C11/419 ,  G11C11/412

    Abstract: A method of memory reset includes precharging bit lines of a memory array, asserting a signal at a reset node to remove the precharge voltage, and selecting write drivers associated with the bit lines associated with columns of the memory array that contain memory cells to be reset, with the assertion of the signal at the reset node also resulting in application of desired logic states to inputs of the selected write drivers to cause those selected write drivers to change a logic state of the bit lines associated with those write drivers. The method continues with asserting each word line associated with a row of the memory that contains memory cells to be reset to write desired logic states to all of the memory cells of the columns and rows of the memory to be reset during a single clock cycle, and then deasserting those word lines.

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