公开(公告)号：US20190034010A1

公开(公告)日：2019-01-31

申请号：US15918014

申请日：2018-03-12

Applicant: Samsung Display Co. Ltd.

Inventor： So La LEE ,  Chi Wook AN ,  Sang Hyun JUN ,  Jong Seok KIM ,  Jae Hyun LEE ,  Eun Ae JUNG

IPC: G06F3/047 ,  G06F3/041

CPC classification number: G06F3/047 ,  G06F3/0412 ,  G06F3/0418 ,  G06F3/044 ,  G06F2203/04112

Abstract: A display device includes a substrate divided into a display area and a peripheral area, a light-emitting element layer on the substrate and including a light-emitting element, a circuit element layer on the substrate and including a circuit element which drives the light-emitting element, an encapsulation film of which portions thereof are respectively in the display area and the peripheral area, and a plurality of sensing electrodes each on the portion of the encapsulation film which is in the display area, including a plurality of first sensing electrodes and a plurality of second sensing electrodes which intersect the first sensing electrodes. Each of the first sensing electrodes includes a plurality of mesh lines intersecting one another in a mesh shape, and widths of the first sensing electrodes increase as a distance of the first sensing electrode from a center of the display area to the peripheral area decreases.

公开(公告)号：US20230411561A1

公开(公告)日：2023-12-21

申请号：US18118486

申请日：2023-03-07

Applicant: Samsung Display Co., LTD.

Inventor： Ki Su JIN ,  Jae Hyun LEE ,  Seul Ki KIM ,  Min Sik JUNG ,  Seung Ha CHOI ,  Jong Bum CHOI

IPC: H01L33/38 ,  H01L33/62 ,  H01L33/00

CPC classification number: H01L33/382 ,  H01L33/62 ,  H01L33/005 ,  H01L2933/0016 ,  H01L2933/0066

Abstract: A display device includes a first base part, a semiconductor layer including a first semiconductor part disposed on the first base part and a second semiconductor part adjacent to a first side of the first semiconductor part in a first direction, a gate insulating layer disposed on the semiconductor layer and including a first gate insulating layer and a second gate insulating layer spaced apart from each other, and a gate conductive layer including a gate electrode disposed on the first gate insulating layer and overlapping the first semiconductor part and a first connecting electrode overlapping the second gate insulating layer and the second semiconductor part. The first connecting electrode includes a protrusion, the second gate insulating layer includes a recess, and the protrusion of the first connecting electrode overlaps the recess of the second gate insulating layer.

公开(公告)号：US20210074793A1

公开(公告)日：2021-03-11

申请号：US16844435

申请日：2020-04-09

Applicant: Samsung Display Co., Ltd.

Inventor： Kyunghyun BAEK ,  Seok Je SEONG ,  Hyeonsik KIM ,  Yoonjee SHIN ,  Jae Hyun LEE ,  Woo Ho JEONG ,  Yoon-Jong CHO

IPC: H01L27/32 ,  H01L29/786

Abstract: A display panel includes two or more gate layers including a plurality of gate patterns extending in a first direction and one or more source-drain layers including a plurality of source-drain patterns extending in a second direction crossing the first direction. The gate patterns of the two or more gate layers are curved or bent along a hole surrounding area corresponding to a periphery of a hole in an active area. The source-drain patterns of the one or more source-drain layers are curved or bent along the hole surrounding area. The gate patterns of at least one of the two or more gate layers overlap the source-drain patterns of at least one of the one or more source-drain layers in a thickness direction of the display panel in the hole surrounding area.

公开(公告)号：US20230062993A1

公开(公告)日：2023-03-02

申请号：US17872948

申请日：2022-07-25

Applicant: Samsung Display Co., LTD.

Inventor： Seul Ki KIM ,  Kwang Soo LEE ,  Jae Hyun LEE ,  Seung Ha CHOI ,  Jong Bum CHOI

IPC: H01L33/38 ,  H01L33/62 ,  H01L33/00

Abstract: A display device includes: a substrate; a first conductive layer on the substrate and including a first pattern; a first insulating layer on the first conductive layer; a semiconductor layer on the first insulating layer and including an active pattern; a second insulating layer on the semiconductor layer; and a second conductive layer on the second insulating layer, wherein the second conductive layer includes a first electrode partially in contact with the active pattern, the first electrode is in contact with the first pattern through a first contact hole, the first contact hole penetrates the first insulating layer and includes a first hole defined by a sidewall of the first insulating layer, and a second hole defined by a sidewall of the active pattern and a sidewall of the second insulating layer, and a width of the second hole is greater than a width of the first hole.

公开(公告)号：US20220392966A1

公开(公告)日：2022-12-08

申请号：US17568504

申请日：2022-01-04

Applicant: Samsung Display Co., Ltd.

Inventor： Kwang Soo LEE ,  Seul Ki KIM ,  Seung Rae KIM ,  Jae Hyun LEE ,  Seung Ha CHOI

IPC: H01L27/32

Abstract: Provided is a display device which comprises a substrate, a first insulating layer disposed on the substrate, a semiconductor layer disposed on the first insulating layer, wherein the semiconductor layer includes an active pattern, a second insulating layer disposed on the semiconductor layer, and a first conductive layer disposed on the second insulating layer. The display device further comprises a gate electrode and source/drain electrodes composed of the same conductive layer, and comprises a semiconductor layer having reduced resistance against an electrical signal applied to the transistor. Thus, reliability of the display device is improved due to the decrease in the resistance of the semiconductor layer.

公开(公告)号：US20210265449A1

公开(公告)日：2021-08-26

申请号：US17109771

申请日：2020-12-02

Applicant: Samsung Display Co., LTD.

Inventor： Se Wan SON ,  Moo Soon KO ,  Kyung Hyun BAEK ,  Seok Je SEONG ,  Jae Hyun LEE ,  Jeong-Soo LEE ,  Ji Seon LEE ,  Yoon-Jong CHO

IPC: H01L27/32

Abstract: A display device includes a first semiconductor layer disposed on a substrate; a first insulating layer disposed on the first semiconductor layer; a scan line disposed on the first insulating layer; a second insulating layer on the scan line; an inverted scan line on the second insulating layer; a third insulating layer disposed on the inverted scan line; a second semiconductor layer disposed on the third insulating layer; a fourth insulating layer disposed on the second semiconductor layer; an initializing voltage line disposed on the fourth insulating layer and overlapping the scan line; a first transistor including a channel disposed in the first semiconductor layer and receiving a gate signal through the scan line; and a second transistor including a channel disposed in the second semiconductor layer and receiving a gate signal through the inverted scan line.