公开(公告)号：US20150097179A1

公开(公告)日：2015-04-09

申请号：US14262761

申请日：2014-04-27

Applicant: Samsung Display Co., LTD.

Inventor： Dae-Ho KIM ,  Hyun-Jae NA ,  Jae-Neung KIM ,  Yu-Gwang JEONG ,  Myoung-Geun CHA ,  Sang-Gab KIM

IPC: H01L27/12

CPC classification number: H01L27/1225 ,  H01L27/1244 ,  H01L27/1248 ,  H01L29/41733

Abstract: A display substrate includes an active pattern, a gate electrode, a first insulation layer and a pixel electrode. The active pattern is disposed on a base substrate. The active pattern includes a metal oxide semiconductor. The gate electrode overlaps the active pattern. The first insulation layer covers the gate electrode and the active pattern, and a contact hole is defined in the first insulation layer. The pixel electrode is electrically connected to the active pattern via the contact hole penetrating the first insulation layer. A first angle defined by a bottom surface of the first insulation layer and a sidewall of the first insulation layer exposed by the contact hole is between about 30° and about 50°.

Abstract translation: 显示基板包括有源图案，栅电极，第一绝缘层和像素电极。 有源图案设置在基底基板上。 有源图案包括金属氧化物半导体。 栅电极与有源图案重叠。 第一绝缘层覆盖栅电极和有源图案，并且在第一绝缘层中限定接触孔。 像素电极经由穿过第一绝缘层的接触孔电连接到有源图案。 由第一绝缘层的底表面和由接触孔露出的第一绝缘层的侧壁限定的第一角度在约30°至约50°之间。

公开(公告)号：US20140054579A1

公开(公告)日：2014-02-27

申请号：US13693423

申请日：2012-12-04

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Dae-Ho KIM ,  Hyun-Jae NA ,  Yong-Su LEE ,  Myoung-Geun CHA ,  Yoon-Ho KHANG ,  Sang-Gab KIM ,  Jae-Neung KIM ,  Se-Hwan YU

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/786 ,  H01L29/4908 ,  H01L29/516 ,  H01L29/66477 ,  H01L29/78618 ,  H01L29/78693

Abstract: A thin film transistor substrate includes a base substrate, an active pattern, a gate insulation pattern and a gate electrode. The active pattern is disposed on the base substrate. The active pattern includes a source electrode, a drain electrode, and a channel disposed between the source electrode and the drain electrode. The gate insulation pattern and the gate electrode overlap with the channel. The gate insulation pattern is disposed between the channel and the gate electrode. The source electrode and the drain electrode each include a fluorine deposition layer.

Abstract translation: 薄膜晶体管基板包括基底基板，有源图案，栅极绝缘图案和栅电极。 有源图案设置在基底基板上。 有源图案包括源电极，漏电极和设置在源电极和漏极之间的沟道。 栅极绝缘图案和栅电极与沟道重叠。 栅极绝缘图案设置在沟道和栅电极之间。 源电极和漏极各自包括氟沉积层。