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公开(公告)号:US20190157210A1
公开(公告)日:2019-05-23
申请号:US16097597
申请日:2016-05-25
申请人: Intel Corporation
IPC分类号: H01L23/538 , H01L23/498 , H01L29/786 , H01L49/02 , H01L21/48
CPC分类号: H01L23/5389 , H01L21/4846 , H01L23/498 , H01L23/49822 , H01L23/49838 , H01L23/522 , H01L23/525 , H01L23/538 , H01L23/5384 , H01L27/1218 , H01L28/60 , H01L29/786 , H01L2224/16225 , H01L2924/15192 , H01L2924/15311
摘要: Disclosed herein are package substrates with integrated components, as well as related apparatuses and methods. For example, in some embodiments, an integrated circuit (IC) package, may include: a substrate having opposing first and second faces, an insulating material disposed between the first and second faces, and a thin film transistor (TFT) disposed between the first and second faces, wherein a conductive portion of the TFT is disposed on a layer of the insulating material, and the conductive portion of the TFT is a gate, source, or drain of the TFT; and a die coupled to the first face of the substrate.
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公开(公告)号:US20190122941A1
公开(公告)日:2019-04-25
申请号:US16096093
申请日:2017-04-26
CPC分类号: H01L22/12 , G01N22/00 , G01N22/02 , H01L21/02565 , H01L21/02631 , H01L29/24 , H01L29/32 , H01L29/786 , H01L29/7869
摘要: A quality evaluation method for an oxide semiconductor thin film includes: selecting a peak value having a largest calculated value and a time constant for the peak value among calculated values obtained by substituting each signal value for respective elapsed times after stopping excitation light irradiation and the corresponding elapsed time into the following Equation (1); and estimating, from the peak value and the time constant, an energy level of defect state and the defect density in the oxide semiconductor thin film: x=(signal value)×(elapsed time for the signal value) Equation 1.
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公开(公告)号:US20190122921A1
公开(公告)日:2019-04-25
申请号:US15793253
申请日:2017-10-25
申请人: GLOBALFOUNDRIES Inc.
IPC分类号: H01L21/768 , H01L29/04
CPC分类号: H01L21/76822 , H01L21/28052 , H01L21/76814 , H01L21/76831 , H01L21/76834 , H01L21/76852 , H01L21/76867 , H01L21/76883 , H01L21/823481 , H01L27/088 , H01L29/045 , H01L29/665 , H01L29/66507 , H01L29/786
摘要: The present disclosure relates to semiconductor devices and manufacturing techniques in which topography-related contact failures may be reduced by providing a dielectric fill material in a late manufacturing stage. In sophisticated semiconductor devices, the material loss in the trench isolation regions may result in significant contact failures, which may be reduced by levelling the device topography, thereby tolerating a significant lateral overlap of contact elements with trench isolation regions.
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4.
公开(公告)号:US20190051756A1
公开(公告)日:2019-02-14
申请号:US16165316
申请日:2018-10-19
IPC分类号: H01L29/786 , H01L29/66 , H01L29/45 , H01L29/24 , H01L27/12 , G02F1/1362 , H01L21/4763 , H01L21/425 , H01L21/027 , H01L21/02 , G02F1/1368
CPC分类号: H01L29/7869 , G02F1/1362 , G02F1/1368 , H01L21/02565 , H01L21/0273 , H01L21/425 , H01L21/47635 , H01L27/1225 , H01L27/1288 , H01L29/24 , H01L29/45 , H01L29/66969 , H01L29/786
摘要: The present application discloses a thin film transistor including a base substrate; an active layer on the base substrate having a channel region, a source electrode contact region, and a drain electrode contact region; an etch stop layer on a side of the channel region distal to the base substrate covering the channel region; a source electrode on a side of the source electrode contact region distal to the base substrate; and a drain electrode on a side of the drain electrode contact region distal to the base substrate. A thickness of the active layer in the source electrode contact region and the drain electrode contact region is substantially the same as a combined thickness of the active layer in the channel region and the etch stop layer.
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5.
公开(公告)号:US20180358359A1
公开(公告)日:2018-12-13
申请号:US15781301
申请日:2016-11-04
申请人: SONY CORPORATION
IPC分类号: H01L27/098 , H01L29/417 , H01L29/778 , H01L29/786 , H01L29/808 , H01L29/812
CPC分类号: H01L27/098 , H01L29/41 , H01L29/417 , H01L29/778 , H01L29/786 , H01L29/808 , H01L29/812
摘要: [Object] To provide a transistor, a semiconductor device, and an electronic apparatus with reduced parasitic resistance. [Solution] A transistor including: a carrier transit layer including a compound semiconductor; a carrier supply layer provided on and in contact with the carrier transit layer and including a compound semiconductor of a different type from the carrier transit layer; a gate electrode provided on the carrier supply layer; and a source electrode and a drain electrode provided on another surface of the carrier transit layer that is opposite to one surface on which the carrier supply layer is provided.
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公开(公告)号:US20180356660A1
公开(公告)日:2018-12-13
申请号:US15781253
申请日:2016-12-02
发明人: Masahiro TOMIDA , Akihiro ODA
IPC分类号: G02F1/1368 , H01L27/12 , H01L29/417 , H01L29/423 , H01L29/786 , H01L21/768
CPC分类号: G02F1/1368 , G09F9/30 , H01L21/28 , H01L21/76829 , H01L27/1225 , H01L27/124 , H01L29/41 , H01L29/417 , H01L29/41733 , H01L29/42384 , H01L29/786 , H01L29/78696
摘要: A plurality of TFTs provided in a peripheral circuit region of an active matrix substrate of an embodiment includes a TFT (10A) in which, when viewed in a direction perpendicular to a substrate (11A), the length in the channel width direction of an oxide semiconductor layer (14A), WAos, is smaller than the length in the channel width direction of a gate electrode (12A), WAg, the length in the channel width direction of a source electrode region (15AR) in which the source electrode (15A) is in contact with the oxide semiconductor layer (14A), WAs, is smaller than the length in the channel width direction of the oxide semiconductor layer (14A), WAos, and the drain electrode (16A) is in contact with the oxide semiconductor layer (14A) in a plurality of drain electrode regions (16AR) arranged in the channel width direction, and the overall length in the channel width direction of the plurality of drain electrode regions (16AR), WAd, is smaller than the length in the channel width direction of the oxide semiconductor layer (14A), WAos.
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公开(公告)号:US20180343006A1
公开(公告)日:2018-11-29
申请号:US15990034
申请日:2018-05-25
IPC分类号: H03K17/687 , H01L29/78 , H01L29/47 , H01L29/739 , H01L29/772 , H01L29/49 , H01L29/51 , H01L29/24 , H01L29/66
CPC分类号: H03K17/687 , H01L29/24 , H01L29/47 , H01L29/495 , H01L29/517 , H01L29/66969 , H01L29/7391 , H01L29/7722 , H01L29/7831 , H01L29/7839 , H01L29/786 , H03K2017/6878 , H03K2217/0018
摘要: The field effect transistor (FET) of the present subject matter comprises a bottom gate electrode, a bottom gate dielectric provided on the bottom gate electrode, a channel layer provided on the bottom gate dielectric. A top portion comprising a source electrode, a drain electrode, a top gate electrode provided, and a top dielectric layer is provided on the channel layer. The channel layer forms Schottky barriers at points of contact with the source and the drain electrode. A back-gate voltage varies a height and a top-gate voltage varies a width of the Schottky barrier. The FET can be programmed to work in two operating modes-tunnelling (providing low power consumption) and thermionic mode (providing high performance). The FET can also be programmed to combine the tunnelling and thermionic mode in a single operating cycle, yielding high performance with low power consumption.
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公开(公告)号:US20180341134A1
公开(公告)日:2018-11-29
申请号:US16055237
申请日:2018-08-06
申请人: Shenzhen China Star Optoelectronics Technology Co. Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
发明人: Juncheng XIAO
IPC分类号: G02F1/1339 , G02F1/1368 , H01L21/02 , H01L21/04 , H01L29/786 , G02F1/01 , G02F1/1362
CPC分类号: G02F1/1339 , G02F1/0107 , G02F1/1368 , G02F2001/13396 , G02F2001/13398 , G02F2001/136231 , G02F2001/13685 , G02F2201/501 , H01L21/02123 , H01L21/02225 , H01L21/0425 , H01L29/458 , H01L29/66757 , H01L29/786 , H01L29/78621 , H01L29/78675
摘要: The disclosure provides a liquid crystal display panel, an array substrate and a manufacturing method thereof. In the method, controllable resistance spacer layers are formed on at least one of a source doped region and a drain doped region of a low temperature polysilicon active layer. When a turn-on signal is not applied to the gate layer, the controllable resistance spacer layers serve as a blocking action for a flowing current; and when the turn-on signal is applied to the gate layer, the controllable resistance spacer layers serve as a conducting action for the flowing current, such that contact regions formed of the controllable resistance spacer layers are respectively connected with the corresponding source layer and the corresponding drain through the controllable resistance spacer layers. Therefore, the disclosure is capable of effectively decreasing a leakage of a thin film transistor.
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9.
公开(公告)号:US20180331131A1
公开(公告)日:2018-11-15
申请号:US15328155
申请日:2016-05-09
发明人: Zijin LIN , Haisheng ZHAO , Xiaoguang PEI , Zhilong PENG , Dongjiang SUN
IPC分类号: H01L27/12 , H01L29/786 , H01L29/66
CPC分类号: H01L27/1288 , H01L27/1262 , H01L29/66742 , H01L29/786
摘要: A method for manufacturing thin film transistor, a method for manufacturing array substrate, an array substrate and a display device are provided. The method for manufacturing thin film transistor includes forming an intermediate layer on a substrate, patterning the intermediate layer to form an intermediate layer reserved region and an intermediate layer unreserved region, where the intermediate layer unreserved region corresponds to a pattern of a first structure layer, forming, on the substrate with a pattern of the intermediate layer, a material layer from which the first structure layer is formed, and removing the intermediate layer, and forming the pattern of the first structure layer through a portion of the material layer remaining on the substrate.
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10.
公开(公告)号:US20180309074A1
公开(公告)日:2018-10-25
申请号:US15565357
申请日:2016-10-10
发明人: Defeng Mao
CPC分类号: H01L51/0566 , G03F7/16 , G03F7/20 , G03F7/26 , H01L29/786 , H01L51/0016 , H01L51/0018 , H01L51/0035 , H01L51/0037 , H01L51/0041 , H01L51/0048 , H01L51/0545 , H01L51/105
摘要: The present application discloses a thin film transistor, a display panel and a display apparatus having the same, and a fabricating method thereof. The thin film transistor includes a base substrate and an active layer on the base substrate having a first portion corresponding to a channel region, a second portion corresponding to a source electrode contact region, and a third portion corresponding to a drain electrode contact region, wherein the second portion and the third portion contain a polymer carbon nanotubes composite including a polymer and a carbon nanotubes material.
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