公开(公告)号：US20140204009A1

公开(公告)日：2014-07-24

申请号：US13929937

申请日：2013-06-28

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Kang Nam Kim ,  Duc-Han Cho ,  You Mee Hyun ,  Jeong-II Kim ,  Jong Woong Chang

IPC: G09G3/36 ,  H03K17/14

CPC classification number: H03K17/145 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/0286 ,  G09G2320/041

Abstract: A gate driver includes a plurality of stages, wherein an n-th stage includes: a pull-up unit configured to output a high voltage of a clock signal as a high voltage of an n-th gate signal; a pull-down unit configured to decrease the high voltage of the n-th gate signal to a first low voltage; a discharging unit configured to discharge a voltage of the first node to a second low voltage lower than the first low voltage; a carry unit configured to output the high voltage of the clock signal as an n-th carry signal; an inverter unit configured to output a signal in synchronization with the clock signal; a first node storage unit configured to maintain the voltage of the first node at the second low voltage; and a second node storage unit configured to maintain the voltage of the second node at the first or second low voltage.

Abstract translation: 栅极驱动器包括多个级，其中第n级包括：上拉单元，被配置为输出时钟信号的高电压作为第n门信号的高电压; 下拉单元，被配置为将第n栅极信号的高电压降低到第一低电压; 放电单元，被配置为将所述第一节点的电压放电到低于所述第一低电压的第二低电压; 输入单元，被配置为输出所述时钟信号的高电压作为第n进位信号; 逆变器单元，被配置为与时钟信号同步地输出信号; 第一节点存储单元，被配置为将所述第一节点的电压维持在所述第二低电压; 以及第二节点存储单元，被配置为将所述第二节点的电压维持在所述第一或第二低电压。