公开(公告)号：US20230335056A1

公开(公告)日：2023-10-19

申请号：US18066981

申请日：2022-12-15

Applicant: Samsung Display Co., LTD.

Inventor： Dae Youn CHO ,  Jong Woo PARK ,  Sang Kil KIM ,  Ji Ho MOON ,  Young Tae CHOI

IPC: G09G3/3233 ,  G09G3/3266

CPC classification number: G09G3/3233 ,  G09G3/3266 ,  G09G2300/0819 ,  G09G2310/0202 ,  G09G2310/0272 ,  G09G2330/028 ,  G09G2310/08 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2320/0233 ,  G09G2320/043

Abstract: A pixel including: a light emitting element; a first transistor connected between a first node and a second node, and to generate a driving current to flow from a first power line to a second power line through the light emitting element; a second transistor connected between a data line and the first node; a third transistor connected between the second node and a third node corresponding to a gate electrode of the first transistor; a fourth transistor connected between the third node and a third power line; a fifth transistor connected between the first power line and the first node; a sixth transistor connected between the second node and a fourth node corresponding to a first electrode of the light emitting element; a seventh transistor connected between the fourth node and a fourth power line; and an eighth transistor connected between the fourth node and a fifth power line.

公开(公告)号：US20210274653A1

公开(公告)日：2021-09-02

申请号：US17158678

申请日：2021-01-26

Applicant: Samsung Display Co., LTD.

Inventor： Chang Woo BYUN ,  Jong Woo PARK ,  Shangu KIM ,  Young Tae CHOI

IPC: H05K1/11 ,  H05K3/32

Abstract: A display device includes a substrate including a display area and a non-display area adjacent to the display area, lower pads disposed in the non-display area of the substrate and spaced apart from each other, upper pads disposed on the lower pads and spaced apart from each other, an anisotropic conductive film disposed between the lower pads and the upper pads, and a circuit film disposed on the upper pads, the circuit film including first lower holes disposed between the upper pads in a plan view, and first upper holes connected to the first lower holes and having radiuses larger than radiuses of the first lower holes. The first upper holes form first openings on an upper surface of the circuit film. A method of manufacturing the display device is provided.

公开(公告)号：US20210134918A1

公开(公告)日：2021-05-06

申请号：US17034852

申请日：2020-09-28

Applicant: Samsung Display Co., LTD.

Inventor： Ji Ho MOON ,  Jong Woo PARK ,  Dae Youn CHO ,  Young Tae CHOI

IPC: H01L27/32

Abstract: An organic light emitting display device may include a first active pattern disposed on a substrate and including a first region, a second region, and a third region; a first gate electrode disposed on the first active pattern and forming a first transistor together with the first region and the second region; a second gate electrode disposed on the first active pattern and forming a second transistor together with the second region and the third region; a third gate electrode disposed on the first gate electrode, overlapping the second region, and forming a storage capacitor together with the first gate electrode; a metal pattern disposed between the first active pattern and the third gate electrode and overlapping the second region; and an organic light emitting diode electrically connected to the first transistor, the second transistor, and the storage capacitor.

公开(公告)号：US20210104558A1

公开(公告)日：2021-04-08

申请号：US16875770

申请日：2020-05-15

Applicant: Samsung Display Co., Ltd.

Inventor： June Hwan KIM ,  Tae Young KIM ,  Jong Woo PARK ,  Young Tae CHOI ,  Hyun Cheol HWANG ,  Ki Ju IM

IPC: H01L27/12 ,  H01L29/786 ,  H01L27/32

Abstract: A display device is provided. The display device comprises a substrate, a first buffer layer on the substrate, a first semiconductor layer on the first buffer layer and including a first active layer, a first gate insulating layer on the first semiconductor layer and the first buffer layer and covering the first active layer, a first conductive layer on the first gate insulating layer and including a first gate electrode, a second conductive layer on the first conductive layer and including a first source/drain electrode, a first interlayer insulating layer on the first conductive layer, a second semiconductor layer on the first interlayer insulating layer and including a second active layer, a second gate insulating layer on the second semiconductor layer and covering the second active layer, and a third conductive layer on the second gate insulating layer and including a second gate electrode and a second source/drain electrode, wherein the first gate insulating layer and the second gate insulating layer include different insulating materials.