公开(公告)号：US20210305427A1

公开(公告)日：2021-09-30

申请号：US17028191

申请日：2020-09-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Deokhan BAE ,  Juhun PARK ,  Myungyoon UM ,  Kwangyong JANG

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/66

Abstract: An integrated circuit device includes a fin-type active region extending on a substrate in a first horizontal direction, a gate line extending on the fin-type active region in a second horizontal direction, first and second source/drain regions arranged on the fin-type active region; a first source/drain contact pattern connected to the first source/drain region and including a first segment having a first height in a vertical direction, a second source/drain contact pattern connected to the second source/drain region and including a second segment having a second height less than the first height in the vertical direction, and an insulating capping line extending on the gate line in the second horizontal direction and including an asymmetric capping portion between the first segment and the second segment, the asymmetric capping portion having a variable thickness in the first horizontal direction.

公开(公告)号：US20180130796A1

公开(公告)日：2018-05-10

申请号：US15689418

申请日：2017-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwichan JUN ,  Deokhan BAE ,  HeonJong SHIN ,  Jaeran JANG ,  Moon Gi CHO ,  YoungWoo CHO

IPC: H01L27/06 ,  H01L23/522 ,  H01L29/06

CPC classification number: H01L27/0629 ,  H01L21/32139 ,  H01L21/823821 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/53295 ,  H01L27/0924 ,  H01L28/20 ,  H01L29/0696 ,  H01L29/785

Abstract: A semiconductor device includes a substrate including a first region and a second region, a cell gate pattern on the first region of the substrate, a dummy gate pattern on the second region of the substrate, a resistor pattern on the second region of the substrate and over the dummy gate pattern, and a connection structure coupled to each of the connection regions. The resistor pattern includes a body region and connection regions at both sides of the body region. The dummy gate pattern overlaps the body region and does not be overlap the connection regions, when viewed in a plan view.