公开(公告)号：US20220109046A1

公开(公告)日：2022-04-07

申请号：US17146136

申请日：2021-01-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak HONG ,  Seunghyun SONG ,  Kang III SEO ,  Hwichan JUN ,  Inchan HWANG

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786 ,  H01L29/417

Abstract: A semiconductor device include: a substrate; a 1st transistor formed above the substrate, the 1st transistor including a 1st channel set of a plurality of 1st nanosheet layers, a 1st gate structure surrounding the 1st nanosheet layers, and 1st and 2nd source/drain regions at both ends of the 1st channel set; and a 2nd transistor formed above the 1st transistor in a vertical direction, the 2nd transistor including a 2nd channel set of a plurality of 2nd nanosheet layers, a 2nd gate structure surrounding the 2nd nanosheet layers, and 3rd and 4th source/drain regions at both ends of the 2nd channel set, wherein the 1st channel set has a greater width than the 2nd channel set, wherein a number of the 1st nanosheet layers is smaller than a number of the 2nd nanosheet layers, and wherein a sum of effective channel widths of the 1st nanosheet layers is substantially equal to a sum of effective channel width of the 2nd nanosheet layers.

公开(公告)号：US20190148503A1

公开(公告)日：2019-05-16

申请号：US16243564

申请日：2019-01-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyoseok CHOI ,  Hwichan JUN ,  Yoonhae KIM ,  Chulsung KIM ,  Heungsik PARK ,  Doo-Young LEE

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: Provided is a semiconductor device including a substrate with an active pattern, a gate electrode crossing the active pattern, a source/drain region in an upper portion of the active pattern at a side of the gate electrode, the source/drain region including a recess region at an upper region thereof, a contact electrically connected to the source/drain region, the contact including a lower portion provided in the recess region, and a metal silicide layer provided at a lower region of the recess region and between the source/drain region and the contact.

公开(公告)号：US20230231015A1

公开(公告)日：2023-07-20

申请号：US18187506

申请日：2023-03-21

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Hwichan JUN ,  Inchan Hwang ,  Byounghak Hong

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L29/417 ,  H01L27/088

CPC classification number: H01L29/0665 ,  H01L29/401 ,  H01L29/66742 ,  H01L29/78696 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/41733 ,  H01L27/088

Abstract: A semiconductor device includes a substrate; a 1st transistor formed above the substrate, and having a 1st transistor stack including a plurality of 1st channel structures, a 1st gate structure surrounding the 1st channel structures, and 1st and 2nd source/drain regions at both ends of the 1st transistor stack in a 1st channel length direction; and a 2nd transistor formed above the 1st transistor in a vertical direction, and having a 2nd transistor stack including a plurality of 2nd channel structures, a 2nd gate structure surrounding the 2nd channel structures, and 3rd and 4th source/drain regions at both ends of the 2nd transistor stack in a 2nd channel length direction, wherein the 3rd source/drain region does not vertically overlap the 1st source/drain region or the 2nd source/drain region, and the 4th source/drain region does not vertically overlap the 1st source/drain region or the 2nd source/drain region.

公开(公告)号：US20220109047A1

公开(公告)日：2022-04-07

申请号：US17148252

申请日：2021-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwichan JUN ,  Inchan Hwang ,  Byounghak Hong

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L29/40 ,  H01L29/66

Abstract: A semiconductor device includes a substrate; a 1st transistor formed above the substrate, and having a 1st transistor stack including a plurality of 1st channel structures, a 1st gate structure surrounding the 1st channel structures, and 1st and 2nd source/drain regions at both ends of the 1st transistor stack in a 1st channel length direction; and a 2nd transistor formed above the 1st transistor in a vertical direction, and having a 2nd transistor stack including a plurality of 2nd channel structures, a 2nd gate structure surrounding the 2nd channel structures, and 3rd and 4th source/drain regions at both ends of the 2nd transistor stack in a 2nd channel length direction, wherein the 3rd source/drain region does not vertically overlap the 1st source/drain region or the 2nd source/drain region, and the 4th source/drain region does not vertically overlap the 1st source/drain region or the 2nd source/drain region.

公开(公告)号：US20230037833A1

公开(公告)日：2023-02-09

申请号：US17970777

申请日：2022-10-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak HONG ,  Seunghyun SONG ,  Kang III SEO ,  Hwichan JUN ,  lnchan HWANG

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device include: a substrate; a 1st transistor formed above the substrate, the 1st transistor including a 1st channel set of a plurality of 1st nanosheet layers, a 1st gate structure surrounding the 1st nanosheet layers, and 1st and 2nd source/drain regions at both ends of the 1st channel set; and a 2nd transistor formed above the 1st transistor in a vertical direction, the 2nd transistor including a 2nd channel set of a plurality of 2nd nanosheet layers, a 2nd gate structure surrounding the 2nd nanosheet layers, and 3rd and 4th source/drain regions at both ends of the 2nd channel set, wherein the 1st channel set has a greater width than the 2nd channel set, wherein a number of the 1st nanosheet layers is smaller than a number of the 2nd nanosheet layers, and wherein a sum of effective channel widths of the 1st nanosheet layers is substantially equal to a sum of effective channel width of the 2nd nanosheet layers.

公开(公告)号：US20190157406A1

公开(公告)日：2019-05-23

申请号：US16014496

申请日：2018-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inchan HWANG ,  Heonjong SHIN ,  Sunghun JUNG ,  Doohyun LEE ,  Hwichan JUN ,  Hakyoon AHN

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L27/092 ,  H01L21/285 ,  H01L29/06 ,  H01L29/66

Abstract: A semiconductor device is disclosed. The semiconductor device may include a substrate including a first active pattern, the first active pattern vertically protruding from a top surface of the substrate, a first source/drain pattern filling a first recess, which is formed in an upper portion of the first active pattern, a first metal silicide layer on the first source/drain pattern, the first metal silicide layer including a first portion and a second portion, which are located on a first surface of the first source/drain pattern, and a first contact in contact with the second portion of the first metal silicide layer. A thickness of the first portion may be different from a thickness of the second portion.

公开(公告)号：US20180130796A1

公开(公告)日：2018-05-10

申请号：US15689418

申请日：2017-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwichan JUN ,  Deokhan BAE ,  HeonJong SHIN ,  Jaeran JANG ,  Moon Gi CHO ,  YoungWoo CHO

IPC: H01L27/06 ,  H01L23/522 ,  H01L29/06

CPC classification number: H01L27/0629 ,  H01L21/32139 ,  H01L21/823821 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/53295 ,  H01L27/0924 ,  H01L28/20 ,  H01L29/0696 ,  H01L29/785

Abstract: A semiconductor device includes a substrate including a first region and a second region, a cell gate pattern on the first region of the substrate, a dummy gate pattern on the second region of the substrate, a resistor pattern on the second region of the substrate and over the dummy gate pattern, and a connection structure coupled to each of the connection regions. The resistor pattern includes a body region and connection regions at both sides of the body region. The dummy gate pattern overlaps the body region and does not be overlap the connection regions, when viewed in a plan view.

公开(公告)号：US20220302134A1

公开(公告)日：2022-09-22

申请号：US17345504

申请日：2021-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inchan HWANG ,  Hwichan JUN

IPC: H01L27/11 ,  H01L27/092 ,  H01L23/528 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device including a static random access memory (SRAM) in a three-dimensional (3D) stack is provided. The semiconductor device includes a first transistor stack including a first channel and a first gate, a second transistor stack including a second channel and a second gate, the second transistor stack being disposed above the first transistor stack, a bit line disposed on a first portion of an upper surface of the first channel, a voltage source disposed on a first portion of an upper surface of the second channel and a first shared contact connecting the first channel to the second channel, where a width of the second channel is less than a width of the first channel.

公开(公告)号：US20210193808A1

公开(公告)日：2021-06-24

申请号：US17175850

申请日：2021-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inchan HWANG ,  Heonjong SHIN ,  Sunghun JUNG ,  Doohyun LEE ,  Hwichan JUN ,  Hakyoon AHN

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L21/285 ,  H01L29/06 ,  H01L27/092 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/78

Abstract: A semiconductor device is disclosed. The semiconductor device may include a substrate including a first active pattern, the first active pattern vertically protruding from a top surface of the substrate, a first source/drain pattern filling a first recess, which is formed in an upper portion of the first active pattern, a first metal silicide layer on the first source/drain pattern, the first metal silicide layer including a first portion and a second portion, which are located on a first surface of the first source/drain pattern, and a first contact in contact with the second portion of the first metal silicide layer. A thickness of the first portion may be different from a thickness of the second portion.

公开(公告)号：US20220359500A1

公开(公告)日：2022-11-10

申请号：US17866066

申请日：2022-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inchan HWANG ,  Hwichan JUN

IPC: H01L27/085 ,  H01L21/8234 ,  H01L21/822

Abstract: An array of multi-stack transistor structures is provided, wherein the multi-stack transistor structures are arranged in a plurality of rows and a plurality of columns in the array, wherein each of the multi-stack transistor structures includes two or more vertically arranged transistor stacks, and wherein a dam structure is formed between adjacent two rows in a same column so that a multi-stack transistor structure in one of the adjacent two rows is electrically isolated from a multi-stack transistor structure in the other of the adjacent two rows in the same column.