公开(公告)号：US11581279B2

公开(公告)日：2023-02-14

申请号：US17229023

申请日：2021-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-il Choi ,  Kwangjin Moon ,  Sujeong Park ,  JuBin Seo ,  Jin Ho An ,  Dong-chan Lim ,  Atsushi Fujisaki

IPC: H01L23/00

Abstract: Disclosed is a semiconductor device including a conductive pattern on a substrate, a passivation layer on the substrate and including an opening that partially exposes the conductive pattern, and a pad structure in the opening of the passivation layer and connected to the conductive pattern. The pad structure includes a first metal layer that fills the opening of the passivation layer and has a width greater than that of the opening, and a second metal layer on the first metal layer. The first metal layer has a first thickness at an outer wall of the first metal layer, a second thickness on a top surface of the passivation layer, and a third thickness on a top surface of the conductive pattern. The second thickness is greater than the first thickness, and the third thickness is greater than the second thickness.

公开(公告)号：US11488860B2

公开(公告)日：2022-11-01

申请号：US16938259

申请日：2020-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Su-jeong Park ,  Dong-chan Lim ,  Kwang-jin Moon ,  Ju-bin Seo ,  Ju-Il Choi ,  Atsushi Fujisaki

IPC: H01L23/48 ,  H01L21/768

Abstract: An integrated circuit device includes a substrate, a landing pad on the substrate, and a through-via structure passing through the substrate and connected to the landing pad. The through-via structure may include a conductive plug, a first conductive barrier layer covering a sidewall and a lower surface of the conductive plug, and a second conductive barrier layer covering a sidewall of the first conductive barrier layer.

公开(公告)号：US11069597B2

公开(公告)日：2021-07-20

申请号：US16366267

申请日：2019-03-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-suk Lee ,  Hak-seung Lee ,  Dong-chan Lim ,  Tae-seong Kim ,  Kwang-jin Moon

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L23/31 ,  H01L23/522 ,  H01L23/532 ,  H01L25/18

Abstract: Semiconductor chips and methods of manufacturing the same are provided. The semiconductor chip includes a substrate, an interlayer insulation layer including a bottom interlayer insulation layer on an upper surface of the substrate and a top interlayer insulation layer on the bottom interlayer insulation layer, an etch stop layer between the bottom interlayer insulation layer and the top interlayer insulation layer, a landing pad on the interlayer insulation layer, and a through via connected to the landing pad through the substrate, the interlayer insulation layer, and the etch stop layer. The etch stop layer is isolated from direct contact with the landing pad.

公开(公告)号：US11018101B2

公开(公告)日：2021-05-25

申请号：US16398888

申请日：2019-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-il Choi ,  Kwang-jin Moon ,  Ju-bin Seo ,  Dong-chan Lim ,  Atsushi Fujisaki ,  Ho-jin Lee

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor device includes a conductive component on a substrate, a passivation layer on the substrate and including an opening that exposes at least a portion of the conductive component, and a pad structure in the opening and located on the passivation layer, the pad structure being electrically connected to the conductive component. The pad structure includes a lower conductive layer conformally extending on an inner sidewall of the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked, a first pad layer on the lower conductive layer and at least partially filling the opening, and a second pad layer on the first pad layer and being in contact with a peripheral portion of the lower conductive layer located on the top surface of the passivation layer.

公开(公告)号：US10325869B2

公开(公告)日：2019-06-18

申请号：US15870044

申请日：2018-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-il Choi ,  Kwang-jin Moon ,  Ju-bin Seo ,  Dong-chan Lim ,  Atsushi Fujisaki ,  Ho-jin Lee

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

Abstract: A semiconductor device includes a conductive component on a substrate, a passivation layer on the substrate and including an opening that exposes at least a portion of the conductive component, and a pad structure in the opening and located on the passivation layer, the pad structure being electrically connected to the conductive component. The pad structure includes a lower conductive layer conformally extending on an inner sidewall of the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked, a first pad layer on the lower conductive layer and at least partially filling the opening, and a second pad layer on the first pad layer and being in contact with a peripheral portion of the lower conductive layer located on the top surface of the passivation layer