Abstract:
A display apparatus, a control method thereof and a recording medium are provided. The display apparatus includes: a display; a communicator configured to communicate with at least one external apparatus; and a processor configured to: control a user interface (UI) to be displayed on the display, the UI including a first item corresponding to the display apparatus and a second item corresponding to the at least one external apparatus and being displayed to distinguish between an external apparatus connected to the display apparatus and an external apparatus disconnected from the display apparatus, and, based on one of at least one of the second item being selected, control the external apparatus corresponding to the selected item to be connected to or disconnected from the display apparatus through the communicator.
Abstract:
An apparatus and method for in-loop filtering based on a largest coding unit (LCU) to reduce an external memory access bandwidth. An in-loop filter may include an external memory to store decoded frames, an internal memory to store pixels in use for deblocking filtering and sample adaptive offset filtering, a horizontal deblocking filter to perform deblocking filtering on input pixels in a horizontal direction with respect to vertical edge boundaries within an input area, a vertical deblocking filter to perform deblocking filtering in a vertical direction with respect to horizontal edge boundaries within the input area, and a sample adaptive offset filter to perform sample adaptive offset filtering.
Abstract:
A reconfigurable processor and an operation method of the reconfigurable processor may include: a status register configured to store a status value used to determine at least one execution mode in a processor; a parallel processing scheduler configured to schedule at least one of a very long instruction word (VLIW) logic and a coarse grained architecture (CGA) logic to be used based on the stored status value; a VLIW register configured to store processed data according to the VLIW logic; and a CGA register configured to store processed data according to the CGA logic.