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公开(公告)号：US20230244632A1
公开(公告)日：2023-08-03
申请号：US18133306
申请日：2023-04-11
IPC分类号： G06F15/173 , G06N3/08 , G06F17/16 , G06F7/57 , G06F7/533 , G06F7/544 , G06F9/38 , G06F13/16 , G06F17/15
CPC分类号： G06F15/17343 , G06N3/08 , G06F17/16 , G06F7/57 , G06F7/5332 , G06F7/5443 , G06F9/3889 , G06F9/3897 , G06F13/1673 , G06F17/15
摘要： A system for calculating. A scratch memory is connected to a plurality of configurable processing elements by a communication fabric including a plurality of configurable nodes. The scratch memory sends out a plurality of streams of data words. Each data word is either a configuration word used to set the configuration of a node or of a processing element, or a data word carrying an operand or a result of a calculation. Each processing element performs operations according to its current configuration and returns the results to the communication fabric, which conveys them back to the scratch memory.
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公开(公告)号：US11698790B2
公开(公告)日：2023-07-11
申请号：US17523633
申请日：2021-11-10
发明人： Luca Iuliano , Simon Nield , Yoong-Chert Foo , Ollie Mower
CPC分类号： G06F9/3861 , G06F9/3016 , G06F9/3834 , G06F9/3838 , G06F9/3867 , G06F9/3889
摘要： Methods and parallel processing units for avoiding inter-pipeline data hazards identified at compile time. For each identified inter-pipeline data hazard the primary instruction and secondary instruction(s) thereof are identified as such and are linked by a counter which is used to track that inter-pipeline data hazard. When a primary instruction is output by the instruction decoder for execution the value of the counter associated therewith is adjusted to indicate that there is hazard related to the primary instruction, and when primary instruction has been resolved by one of multiple parallel processing pipelines the value of the counter associated therewith is adjusted to indicate that the hazard related to the primary instruction has been resolved. When a secondary instruction is output by the decoder for execution, the secondary instruction is stalled in a queue associated with the appropriate instruction pipeline if at least one counter associated with the primary instructions from which it depends indicates that there is a hazard related to the primary instruction.
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公开(公告)号：US20180217837A1
公开(公告)日：2018-08-02
申请号：US15925957
申请日：2018-03-20
发明人： Srinivas Lingam , Seok-Jun Lee , Johann Zipperer , Manish Goel
CPC分类号： G06F9/3013 , G06F9/3001 , G06F9/30036 , G06F9/30098 , G06F9/3877 , G06F9/3889 , G06F13/1678 , G06F13/4018 , G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： An apparatus for a low energy accelerator processor architecture is disclosed. An example arrangement is an integrated circuit that includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory; a low energy accelerator processor configured to execute instruction words received on the system bus and having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, wherein each of the execution units is configured to perform operations responsive to retrieved instruction words; and a data register file comprising a set of data registers coupled to the plurality of execution units, wherein the registers are coupled to selected ones of the plurality of execution units. Additional methods and apparatus are disclosed.
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公开(公告)号：US20180189062A1
公开(公告)日：2018-07-05
申请号：US15396177
申请日：2016-12-30
申请人： Intel Corporation
IPC分类号： G06F9/30 , G06F12/1009 , G06F12/1027
CPC分类号： G06F9/3016 , G06F3/06 , G06F9/3004 , G06F9/30043 , G06F9/30058 , G06F9/30101 , G06F9/3885 , G06F9/3889 , G06F9/3891 , G06F12/1009 , G06F12/1027 , G06F15/76 , G06F2212/205 , G06F2212/502
摘要： A processor of an aspect includes a decode unit to decode an instruction. The instruction is to indicate a source memory address information, and is to indicate a destination architecturally-visible storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to store a result in the destination architecturally-visible storage location. The result to indicate whether a logical memory address corresponding to the source memory address information is in a persistent memory. Other processors, methods, systems, and instructions are disclosed.
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公开(公告)号：US09996361B2
公开(公告)日：2018-06-12
申请号：US14757609
申请日：2015-12-23
申请人： Intel Corporation
CPC分类号： G06F9/3889 , G06F9/30 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30112 , G06F9/3861 , G06F9/3887
摘要： A processor comprises a first register to store a plurality of data items at a plurality of positions within the first register, a second register, and an execution unit, operatively coupled to the first register and the second register, the execution unit comprising a logic circuit implementing a sort instruction for sorting the plurality of data items stored in the first register in an order of data item values, and storing, in the second register, a plurality of indices, wherein each index identifies a position associated with a data item stored in the first register prior to the sorting.
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6.发明申请公开(公告)号：US20180137081A1
公开(公告)日：2018-05-17
申请号：US15853323
申请日：2017-12-22
申请人： Intel Corporation
发明人： Mohammad A. Abdallah
CPC分类号： G06F15/8007 , G06F7/483 , G06F7/5318 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30109 , G06F9/3012 , G06F9/30123 , G06F9/30141 , G06F9/3016 , G06F9/30181 , G06F9/30189 , G06F9/3824 , G06F9/3828 , G06F9/3838 , G06F9/3851 , G06F9/3853 , G06F9/3867 , G06F9/3885 , G06F9/3887 , G06F9/3889 , G06F9/3891 , G06F15/80
摘要： A matrix of execution blocks form a set of rows and columns. The rows support parallel execution of instructions and the columns support execution of dependent instructions. The matrix of execution blocks process a single block of instructions specifying parallel and dependent instructions.
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公开(公告)号：US09959202B2
公开(公告)日：2018-05-01
申请号：US14855803
申请日：2015-09-16
发明人： Jan Van Lunteren , Heiner Giefers
CPC分类号： G06F12/02 , G06F1/3275 , G06F9/265 , G06F9/30007 , G06F9/3004 , G06F9/3824 , G06F9/3836 , G06F9/3889 , G06F15/7821 , G06F15/80 , Y02D10/13 , Y02D10/14
摘要： A computing memory includes an execution unit and an access processor coupled with a memory system, where the execution unit and the access processor are logically separated units. The execution unit is for processing operand data. The access processor is for providing operand data and configuration data to the execution unit. The access processor reads operand data from the memory system and sends the operand data to the execution unit. The execution unit executes the operand data according to the provided configuration data. The access processor includes information about execution times of operations of the execution unit for the provided configuration. The access processor reserves time-slots for writing execution unit results provided by the execution unit into selected locations in the memory system based on the information about the execution times, upon sending at least one of the operand data and the configuration data to the execution unit.
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公开(公告)号：US09886416B2
公开(公告)日：2018-02-06
申请号：US14733827
申请日：2015-06-08
申请人： Intel Corporation
发明人： Mohammad A. Abdallah
CPC分类号： G06F15/8007 , G06F7/483 , G06F7/5318 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30109 , G06F9/3012 , G06F9/30123 , G06F9/30141 , G06F9/3016 , G06F9/30181 , G06F9/30189 , G06F9/3824 , G06F9/3828 , G06F9/3838 , G06F9/3851 , G06F9/3853 , G06F9/3867 , G06F9/3885 , G06F9/3887 , G06F9/3889 , G06F9/3891 , G06F15/80
摘要： A matrix of execution blocks form a set of rows and columns. The rows support parallel execution of instructions and the columns support execution of dependent instructions. The matrix of execution blocks process a single block of instructions specifying parallel and dependent instructions.
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公开(公告)号：US09870315B2
公开(公告)日：2018-01-16
申请号：US15417676
申请日：2017-01-27
发明人： Jan Van Lunteren , Heiner Giefers
CPC分类号： G06F12/02 , G06F1/3275 , G06F9/265 , G06F9/30007 , G06F9/3004 , G06F9/3824 , G06F9/3836 , G06F9/3889 , G06F15/7821 , G06F15/80 , Y02D10/13 , Y02D10/14
摘要： A computing memory includes an execution unit and an access processor coupled with a memory system, where the execution unit and the access processor are logically separated units. The execution unit is for processing operand data. The access processor is for providing operand data and configuration data to the execution unit. The access processor reads operand data from the memory system and sends the operand data to the execution unit. The execution unit executes the operand data according to the provided configuration data. The access processor includes information about execution times of operations of the execution unit for the provided configuration. The access processor reserves time-slots for writing execution unit results provided by the execution unit into selected locations in the memory system based on the information about the execution times, upon sending at least one of the operand data and the configuration data to the execution unit.
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公开(公告)号：US20170315814A1
公开(公告)日：2017-11-02
申请号：US15224469
申请日：2016-07-29
发明人： Aaron L. Smith , Jan S. Gray
IPC分类号： G06F9/38 , G06F12/0875 , G06F9/30
CPC分类号： G06F9/3836 , G06F9/3005 , G06F9/3016 , G06F9/3017 , G06F9/30181 , G06F9/30185 , G06F9/3802 , G06F9/3818 , G06F9/3834 , G06F9/3838 , G06F9/3855 , G06F9/3873 , G06F9/3885 , G06F9/3889 , G06F9/3897 , G06F12/0875 , G06F15/7867
摘要： Apparatus and methods are disclosed for implementing block-based processors including field programmable gate-array implementations. In one example of the disclosed technology, a block-based processor includes an instruction decoder configured to generate decoded ready dependencies for a transactional block of instructions, where each of the instructions is associated with a different instruction identifier encoded in the transactional block. The processor further includes an instruction scheduler configured to issue an instruction from the set of transactional block of instructions out of order. The instruction is issued based on determining that decoded ready state dependencies for an instruction are satisfied. The determining includes accessing storage with the decoded ready dependencies indexed with a respective instruction identifier that is encoded in the transactional block of instructions.
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