公开(公告)号：US20190244896A1

公开(公告)日：2019-08-08

申请号：US16008319

申请日：2018-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eui Bok LEE ,  Jong Min BAEK ,  Sang Hoon AHN ,  Hyeok Sang OH

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/02 ,  H01L23/532

Abstract: A semiconductor device includes a lower insulating layer disposed on a substrate. A conductive pattern is formed in the lower insulating layer. A middle insulating layer is disposed on the lower insulating layer and the conductive pattern. A via control region is formed in the middle insulating layer. An upper insulating layer is disposed on the middle insulating layer and the via control region. A via plug is formed to pass through the via control region and to be connected to the conductive pattern. The via control region has a lower etch rate than the middle insulating layer.