公开(公告)号：US20230255021A1

公开(公告)日：2023-08-10

申请号：US18137169

申请日：2023-04-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngjun Kim ,  Seokhyun Kim ,  Jinhyung Park ,  Hoju Song ,  Hyeran Lee ,  Bongsoo Kim ,  Sungwoo Kim

IPC: H10B12/00 ,  H01L21/768

CPC classification number: H10B12/485 ,  H01L21/76829 ,  H10B12/09 ,  H10B12/315 ,  H10B12/0335

Abstract: A semiconductor device includes a bit line structure, first and second capping patterns, first and second contact plug structures, and a capacitor. The bit line structure extends on a cell region and a dummy region. The first capping pattern is adjacent the bit line structure on the cell region. The second capping pattern is adjacent the bit line structure on the dummy region. The first contact plug structure is adjacent the bit line structure and the first capping pattern on the cell region, and includes a lower contact plug and a first upper contact plug sequentially stacked. The second contact plug structure is adjacent the bit line structure and the second capping pattern on the dummy region, and includes a dummy lower contact plug and a second upper contact plug sequentially stacked. The capacitor contacts an upper surface of the first contact plug structure on the cell region.

公开(公告)号：US11678478B2

公开(公告)日：2023-06-13

申请号：US17667697

申请日：2022-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngjun Kim ,  Seokhyun Kim ,  Jinhyung Park ,  Hoju Song ,  Hyeran Lee ,  Bongsoo Kim ,  Sungwoo Kim

IPC: H01L27/10 ,  H01L27/108 ,  H01L21/768

CPC classification number: H01L27/10888 ,  H01L21/76829 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10894

Abstract: A semiconductor device includes a bit line structure, first and second capping patterns, first and second contact plug structures, and a capacitor. The bit line structure extends on a cell region and a dummy region. The first capping pattern is adjacent the bit line structure on the cell region. The second capping pattern is adjacent the bit line structure on the dummy region. The first contact plug structure is adjacent the bit line structure and the first capping pattern on the cell region, and includes a lower contact plug and a first upper contact plug sequentially stacked. The second contact plug structure is adjacent the bit line structure and the second capping pattern on the dummy region, and includes a dummy lower contact plug and a second upper contact plug sequentially stacked. The capacitor contacts an upper surface of the first contact plug structure on the cell region.

公开(公告)号：US11264392B2

公开(公告)日：2022-03-01

申请号：US16832268

申请日：2020-03-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngjun Kim ,  Seokhyun Kim ,  Jinhyung Park ,  Hoju Song ,  Hyeran Lee ,  Bongsoo Kim ,  Sungwoo Kim

IPC: H01L29/00 ,  H01L27/108

Abstract: A semiconductor device includes a bit line structure, first and second capping patterns, first and second contact plug structures, and a capacitor. The bit line structure extends on a cell region and a dummy region. The first capping pattern is adjacent the bit line structure on the cell region. The second capping pattern is adjacent the bit line structure on the dummy region. The first contact plug structure is adjacent the bit line structure and the first capping pattern on the cell region, and includes a lower contact plug and a first upper contact plug sequentially stacked. The second contact plug structure is adjacent the bit line structure and the second capping pattern on the dummy region, and includes a dummy lower contact plug and a second upper contact plug sequentially stacked. The capacitor contacts an upper surface of the first contact plug structure on the cell region.