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    Semiconductor memory device and method of manufacturing the same
    1.
    发明授权
    Semiconductor memory device and method of manufacturing the same 有权

    公开(公告)号：US11183500B2

    公开(公告)日：2021-11-23

    申请号：US16826655

    申请日：2020-03-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hoju Song ,  Seokhyun Kim ,  Youngjun Kim ,  Jinhyung Park ,  Hyeran Lee ,  Bongsoo Kim ,  Sungwoo Kim

    IPC: H01L27/108

    Abstract: A method of manufacturing a semiconductor memory device includes forming bit line structures extending in a first horizontal direction on a substrate, and insulating spacer structures covering opposite sidewalls of each bit line structure, forming a preliminary buried contact material layer and a mold layer to respectively fill lower and upper portions of a space between a pair of insulating spacer structures, patterning the mold layer and the preliminary buried contact material layer into mold patterns spaced apart from each other in a second horizontal direction and buried contacts spaced apart from each other in the second horizontal direction, forming insulating fences among the mold patterns separated from each other and among the buried contacts separated from each other, removing the mold patterns to expose the buried contacts, and forming landing pads on the exposed buried contacts, each landing pad connected to a corresponding one of the exposed buried contacts.

    SSEMICONDUCTOR DEVICES
    3.
    发明申请
    SSEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20220254787A1

    公开(公告)日：2022-08-11

    申请号：US17667697

    申请日：2022-02-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Youngjun Kim ,  Seokhyun Kim ,  Jinhyung Park ,  Hoju Song ,  Hyeran Lee ,  Bongsoo Kim ,  Sungwoo Kim

    IPC: H01L27/108

    Abstract: A semiconductor device includes a bit line structure, first and second capping patterns, first and second contact plug structures, and a capacitor. The bit line structure extends on a cell region and a dummy region. The first capping pattern is adjacent the bit line structure on the cell region. The second capping pattern is adjacent the bit line structure on the dummy region. The first contact plug structure is adjacent the bit line structure and the first capping pattern on the cell region, and includes a lower contact plug and a first upper contact plug sequentially stacked. The second contact plug structure is adjacent the bit line structure and the second capping pattern on the dummy region, and includes a dummy lower contact plug and a second upper contact plug sequentially stacked. The capacitor contacts an upper surface of the first contact plug structure on the cell region.

    Semiconductor memory device and a method of fabricating the same
    4.
    发明授权
    Semiconductor memory device and a method of fabricating the same 有权

    公开(公告)号：US11251188B2

    公开(公告)日：2022-02-15

    申请号：US16990305

    申请日：2020-08-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seok-Hyun Kim ,  Joon Young Kang ,  Youngjun Kim ,  Jinhyung Park ,  Ho-Ju Song ,  Sang-Jun Lee ,  Hyeran Lee ,  Bong-Soo Kim ,  Sungwoo Kim

    IPC: H01L27/088 ,  H01L21/00 ,  H01L27/108

    Abstract: A semiconductor memory device including: a substrate including a cell array region and a boundary region; a first recess region at an upper portion of the substrate in the cell array region; a first bit line extending onto the boundary region and crossing the first recess region; a bit line contact in the first recess region and contacting the first bit line; a second bit line spaced apart from the first recess region and adjacent to the first bit line, the second bit line crossing the cell array region and the boundary region; a cell buried insulation pattern between a side surface of the first bit line contact and an inner wall of the first recess region; and a boundary buried insulation pattern covering sidewalls of the first bit line and the second bit line in the boundary region and including a same material as the cell buried insulation pattern.

    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    5.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20210035983A1

    公开(公告)日：2021-02-04

    申请号：US16826655

    申请日：2020-03-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hoju Song ,  Seokhyun Kim ,  Youngjun Kim ,  Jinhyung Park ,  Hyeran Lee ,  Bongsoo Kim ,  Sungwoo Kim

    IPC: H01L27/108

    Abstract: A method of manufacturing a semiconductor memory device includes forming bit line structures extending in a first horizontal direction on a substrate, and insulating spacer structures covering opposite sidewalls of each bit line structure, forming a preliminary buried contact material layer and a mold layer to respectively fill lower and upper portions of a space between a pair of insulating spacer structures, patterning the mold layer and the preliminary buried contact material layer into mold patterns spaced apart from each other in a second horizontal direction and buried contacts spaced apart from each other in the second horizontal direction, forming insulating fences among the mold patterns separated from each other and among the buried contacts separated from each other, removing the mold patterns to expose the buried contacts, and forming landing pads on the exposed buried contacts, each landing pad connected to a corresponding one of the exposed buried contacts.

    Semiconductor memory devices
    7.
    发明授权
    Semiconductor memory devices 有权

    公开(公告)号：US11968824B2

    公开(公告)日：2024-04-23

    申请号：US18137169

    申请日：2023-04-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Youngjun Kim ,  Seokhyun Kim ,  Jinhyung Park ,  Hoju Song ,  Hyeran Lee ,  Sungwoo Kim ,  Bongsoo Kim

    IPC: H01L27/10 ,  H01L21/768 ,  H10B12/00

    CPC classification number: H10B12/485 ,  H01L21/76829 ,  H10B12/0335 ,  H10B12/09 ,  H10B12/315

    Abstract: A semiconductor device includes a bit line structure, first and second capping patterns, first and second contact plug structures, and a capacitor. The bit line structure extends on a cell region and a dummy region. The first capping pattern is adjacent the bit line structure on the cell region. The second capping pattern is adjacent the bit line structure on the dummy region. The first contact plug structure is adjacent the bit line structure and the first capping pattern on the cell region, and includes a lower contact plug and a first upper contact plug sequentially stacked. The second contact plug structure is adjacent the bit line structure and the second capping pattern on the dummy region, and includes a dummy lower contact plug and a second upper contact plug sequentially stacked. The capacitor contacts an upper surface of the first contact plug structure on the cell region.

    SEMICONDUCTOR DEVICES
    9.
    发明公开
    SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20230255021A1

    公开(公告)日：2023-08-10

    申请号：US18137169

    申请日：2023-04-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Youngjun Kim ,  Seokhyun Kim ,  Jinhyung Park ,  Hoju Song ,  Hyeran Lee ,  Bongsoo Kim ,  Sungwoo Kim

    IPC: H10B12/00 ,  H01L21/768

    CPC classification number: H10B12/485 ,  H01L21/76829 ,  H10B12/09 ,  H10B12/315 ,  H10B12/0335

    Abstract: A semiconductor device includes a bit line structure, first and second capping patterns, first and second contact plug structures, and a capacitor. The bit line structure extends on a cell region and a dummy region. The first capping pattern is adjacent the bit line structure on the cell region. The second capping pattern is adjacent the bit line structure on the dummy region. The first contact plug structure is adjacent the bit line structure and the first capping pattern on the cell region, and includes a lower contact plug and a first upper contact plug sequentially stacked. The second contact plug structure is adjacent the bit line structure and the second capping pattern on the dummy region, and includes a dummy lower contact plug and a second upper contact plug sequentially stacked. The capacitor contacts an upper surface of the first contact plug structure on the cell region.

    Semiconductor devices
    10.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US11678478B2

    公开(公告)日：2023-06-13

    申请号：US17667697

    申请日：2022-02-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Youngjun Kim ,  Seokhyun Kim ,  Jinhyung Park ,  Hoju Song ,  Hyeran Lee ,  Bongsoo Kim ,  Sungwoo Kim

    IPC: H01L27/10 ,  H01L27/108 ,  H01L21/768

    CPC classification number: H01L27/10888 ,  H01L21/76829 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10894

    Abstract: A semiconductor device includes a bit line structure, first and second capping patterns, first and second contact plug structures, and a capacitor. The bit line structure extends on a cell region and a dummy region. The first capping pattern is adjacent the bit line structure on the cell region. The second capping pattern is adjacent the bit line structure on the dummy region. The first contact plug structure is adjacent the bit line structure and the first capping pattern on the cell region, and includes a lower contact plug and a first upper contact plug sequentially stacked. The second contact plug structure is adjacent the bit line structure and the second capping pattern on the dummy region, and includes a dummy lower contact plug and a second upper contact plug sequentially stacked. The capacitor contacts an upper surface of the first contact plug structure on the cell region.

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