公开(公告)号：US09064731B2

公开(公告)日：2015-06-23

申请号：US14255365

申请日：2014-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Je-Min Park

IPC: H01L27/108 ,  H01L21/768

CPC classification number: H01L27/10855 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10888

Abstract: A semiconductor device including a substrate, the substrate including active regions; a pair of conductive lines spaced apart from the substrate such that an insulating layer is between the substrate and the pair of conductive lines; insulating spacers covering side walls of each of the pair of conductive lines such that contact holes having first widths in a first direction are defined between the pair of conductive lines; upper insulating patterns on the pair of conductive lines, the upper insulating patterns defining landing pad holes connected to the contact holes such that the landing pad holes have second widths in the first direction that are greater than the first widths; contact structures including contact plugs connected to the active regions by passing through the insulating layer, and first landing pads connected to the contact plugs, the first landing pads being in the landing pads holes such that the first landing pads vertically overlap with one of the pair of conductive lines; and capacitor lower electrodes connected to the contact structures.

Abstract translation: 一种包括衬底的半导体器件，所述衬底包括有源区; 一对与衬底间隔开的导电线，使得绝缘层位于衬底和一对导电线之间; 绝缘间隔物，覆盖所述一对导线中的每一个的侧壁，使得在所述一对导线之间限定具有第一方向的第一宽度的接触孔; 所述一对导线上的上绝缘图案，所述上绝缘图案限定着接地焊盘孔连接到所述接触孔，使得所述着陆焊盘孔具有在所述第一方向上具有大于所述第一宽度的第二宽度; 接触结构，包括通过穿过绝缘层连接到有源区的接触插塞，以及连接到接触插塞的第一着陆焊盘，第一着陆焊盘位于着陆焊盘孔中，使得第一着陆焊盘与该对中的一个垂直重叠 的导线; 和连接到接触结构的电容器下电极。

公开(公告)号：US20150132945A1

公开(公告)日：2015-05-14

申请号：US14303142

申请日：2014-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Je-Min Park

IPC: H01L21/768

CPC classification number: H01L27/10897 ,  H01L21/7682 ,  H01L21/76885 ,  H01L23/5283 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices and methods of fabricating the same are disclosed. The methods include forming a first interlayer insulating layer and a conductive contact plug that penetrates the first interlayer insulating layer, forming a second interlayer insulating layer and a first interlayer wiring on the first interlayer insulating layer. The first interlayer wiring penetrates the second interlayer insulating layer and overlaps the first metal contact plug. The second interlayer insulating layer is etched using the first interlayer wiring as a mask until the first metal contact plug is exposed, and an exposed portion of the conductive contact plug is etched using the first interlayer wiring as the mask.

Abstract translation: 公开了半导体器件及其制造方法。 所述方法包括在第一层间绝缘层上形成穿透第一层间绝缘层的第一层间绝缘层和导电接触塞，形成第二层间绝缘层和第一层间布线。 第一层间布线穿透第二层间绝缘层并与第一金属接触插塞重叠。 使用第一层间布线作为掩模蚀刻第二层间绝缘层，直到第一金属接触插塞露出，并且使用第一层间布线作为掩模来蚀刻导电接触插塞的暴露部分。