公开(公告)号：US20250087647A1

公开(公告)日：2025-03-13

申请号：US18818203

申请日：2024-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jing Cheng LIN ,  Youngkun Jee

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/36 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/16 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor package includes a lower redistribution structure, an internal semiconductor chip on the lower redistribution structure and including first connection pads on a lower surface of the internal semiconductor chip, conductive posts connected to the lower redistribution structure, an encapsulant surrounding a side surface of each of the conductive posts, surrounding a side surface of the internal semiconductor chip, and covering an upper surface of the internal semiconductor chip, upper trace pads on the encapsulant and respectively connected to ends of the conductive posts, an external semiconductor device on the encapsulant, the external semiconductor device including second connection pads on a lower surface of the external semiconductor device and respectively connected to the upper trace pads, and a heat dissipation structure on the encapsulant and laterally spaced apart from the external semiconductor device.

公开(公告)号：US20250079365A1

公开(公告)日：2025-03-06

申请号：US18667796

申请日：2024-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jing Cheng LIN ,  Youngkun JEE

IPC: H01L23/00

Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip hybrid-bonded to the first semiconductor chip. The first semiconductor chip includes first main pads, which are apart from each other, and a first bonding insulation layer extending around the first main pads. Each of the first main pads includes first sub main pads apart from each other. The second semiconductor chip includes second main pads, which are spaced apart from each other, and a second bonding insulation layer extending around the second main pads. The second main pads are aligned with the first main pads. Each of the second main pads includes second sub main pads spaced apart from each other. Each of the second sub main pads is bonded to a respective one of the first sub main pads. The second bonding insulation layer is bonded to the first bonding insulation layer.

公开(公告)号：US20240429203A1

公开(公告)日：2024-12-26

申请号：US18427470

申请日：2024-01-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jing Cheng LIN ,  Youngkun JEE

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538

Abstract: Provided is a semiconductor package including a first redistribution structure, a second redistribution structure on the first redistribution structure, a plurality of semiconductor chips on an upper surface of the second redistribution structure, a bridge chip on a lower surface of the second redistribution structure, and a first molding layer between the first redistribution structure and the second redistribution structure and adjacent to the bridge chip, wherein the first molding layer is between the bridge chip and the first redistribution structure.

公开(公告)号：US20240429174A1

公开(公告)日：2024-12-26

申请号：US18750274

申请日：2024-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jing Cheng LIN ,  Kwangbae KIM ,  Hyunchul JUNG ,  Youngkun JEE

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor package according to an embodiment includes a first semiconductor chip, a second semiconductor chip, a first dielectric film surrounding the first semiconductor chip and the second semiconductor chip; first vias; second vias; a bridge chip; a second dielectric film surrounding the bridge chip and having an upper surface and a lower surface opposite to the upper surface; and a third via, some of the first vias are electrically connected to some of the bridge chip pads, some of the second vias are electrically connected to others of the bridge chip pads, and the passivation layer includes a same material as a material of the first dielectric film.

公开(公告)号：US20250014974A1

公开(公告)日：2025-01-09

申请号：US18750209

申请日：2024-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Jing Cheng LIN ,  Youngkun JEE

IPC: H01L23/498 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L25/16 ,  H10B80/00

Abstract: A semiconductor package and a method of manufacturing the semiconductor package are provided. A method includes: forming a seed layer; forming a first photoresist pattern on the seed layer; forming a metal pad on the seed layer by using the first photoresist pattern; forming a second photoresist pattern on the seed layer; forming a conductive post on the seed layer by using the second photoresist pattern; providing, on the metal pad, a first semiconductor chip on which a conductive pillar and an insulating material layer surrounding a sidewall of the conductive pillar are formed; bonding the first semiconductor chip to the metal pad by using a connection terminal; forming a first molding layer surrounding the first semiconductor chip; removing the connection terminal and the metal pad; and forming a redistribution structure connected to the conductive pillar.

公开(公告)号：US20250006618A1

公开(公告)日：2025-01-02

申请号：US18634101

申请日：2024-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jing Cheng LIN ,  Youngkun JEE

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/48 ,  H01L25/18

Abstract: Provided is a semiconductor package including a package substrate, a redistribution structure including a single-layered insulating layer positioned above the package substrate, and a plurality of horizontal redistribution structures embedded in the insulating layer and arranged side-by-side in a first horizontal direction parallel to an upper surface of the package substrate and in a second horizontal direction perpendicular to the first horizontal direction, external connection terminals arranged below the redistribution structure, and a semiconductor chip provided on the redistribution structure and including a chip body and chip connection terminals arranged below the chip body, wherein each of the plurality of horizontal redistribution structures includes a via passing through the insulating layer, and a tracer pattern formed integrally with the via and inclined and long from the first horizontal direction and the second horizontal direction.

公开(公告)号：US20250006582A1

公开(公告)日：2025-01-02

申请号：US18403462

申请日：2024-01-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jing Cheng LIN ,  Youngkun Jee

IPC: H01L23/36 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H10B80/00

Abstract: A semiconductor package is provided. The semiconductor package includes: a redistribution substrate; a first semiconductor chip provided on a right portion, in a first direction, of the redistribution substrate; a through-post provided on the redistribution substrate in a region adjacent to a left side, in the first direction, of the first semiconductor chip; a heat dissipation chip provided on the first semiconductor chip; and a second semiconductor device provided adjacent to the heat dissipation chip on the through-post. A metal pad and an adhesive layer are provided between the heat dissipation chip and the first semiconductor chip.

公开(公告)号：US20240429222A1

公开(公告)日：2024-12-26

申请号：US18654758

申请日：2024-05-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jing Cheng LIN ,  Youngkun Jee

IPC: H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/367 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

Abstract: A method of manufacturing a semiconductor package includes bonding a first semiconductor chip and a bridge structure onto a carrier structure; bonding a second semiconductor chip and a third semiconductor chip onto the bridge structure, the second semiconductor chip and the third semiconductor chip being apart from each other in a horizontal direction; and forming a plurality of connection bumps on the second semiconductor chip and the third semiconductor chip.

公开(公告)号：US20240429200A1

公开(公告)日：2024-12-26

申请号：US18665102

申请日：2024-05-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jing Cheng LIN ,  Youngkun JEE

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/538 ,  H10B80/00

Abstract: A semiconductor package includes a redistribution structure including: a passivation layer; an under bump metallurgy (UBM) layer on a portion of a lower surface of the passivation layer; and a conductive layer in contact with the UBM layer and exposed from an upper surface of the passivation layer opposite to the lower surface of the passivation layer. The semiconductor package further includes: a bridge chip on the redistribution structure and including a bridge chip pad; a first molding layer sealing the bridge chip on the redistribution structure; conductive posts spaced apart from each other in a horizontal direction within the first molding layer, the bridge chip being between the conductive posts and each of the conductive posts; and a semiconductor chips on the first molding layer and the bridge chip, each of the semiconductor chips including a chip pad and a solder bump.