公开(公告)号：US20250125302A1

公开(公告)日：2025-04-17

申请号：US18808869

申请日：2024-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jing Cheng LIN ,  Youngkun Jee

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/31 ,  H10B80/00

Abstract: A semiconductor package includes a first semiconductor chip including a plurality of upper pads, a non-conductive support layer on a top surface of the first semiconductor chip and including a plurality of openings, a second semiconductor chip on the first semiconductor chip and including a plurality of lower pads, a plurality of chip connecting terminals extending between the plurality of upper pads and the plurality of lower pads, and an insulation adhesive layer between the first semiconductor chip and the second semiconductor chip and at least partially covering the plurality of chip connecting terminals and the non-conductive support layer. A top surface of the non-conductive support layer is disposed closer to a bottom surface of the second semiconductor chip than top surfaces of the plurality of upper pads are disposed to the bottom surface of the second semiconductor chip.

公开(公告)号：US20250006582A1

公开(公告)日：2025-01-02

申请号：US18403462

申请日：2024-01-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jing Cheng LIN ,  Youngkun Jee

IPC: H01L23/36 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H10B80/00

Abstract: A semiconductor package is provided. The semiconductor package includes: a redistribution substrate; a first semiconductor chip provided on a right portion, in a first direction, of the redistribution substrate; a through-post provided on the redistribution substrate in a region adjacent to a left side, in the first direction, of the first semiconductor chip; a heat dissipation chip provided on the first semiconductor chip; and a second semiconductor device provided adjacent to the heat dissipation chip on the through-post. A metal pad and an adhesive layer are provided between the heat dissipation chip and the first semiconductor chip.

公开(公告)号：US20240429222A1

公开(公告)日：2024-12-26

申请号：US18654758

申请日：2024-05-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jing Cheng LIN ,  Youngkun Jee

IPC: H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/367 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

Abstract: A method of manufacturing a semiconductor package includes bonding a first semiconductor chip and a bridge structure onto a carrier structure; bonding a second semiconductor chip and a third semiconductor chip onto the bridge structure, the second semiconductor chip and the third semiconductor chip being apart from each other in a horizontal direction; and forming a plurality of connection bumps on the second semiconductor chip and the third semiconductor chip.

公开(公告)号：US20230119548A1

公开(公告)日：2023-04-20

申请号：US17873990

申请日：2022-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyoeun Kim ,  Juhyeon Kim ,  Wonil Lee ,  Youngkun Jee

IPC: H01L23/00 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor chip including a first substrate and a first bonding layer disposed on the first substrate, and having a flat first outer surface provided by the first bonding layer; and a second semiconductor chip disposed on the first outer surface of the first semiconductor chip, including a second substrate and a second bonding layer disposed on the second substrate, and having a flat second outer surface provided by the second bonding layer and contacting the first outer surface of the first semiconductor chip. The first bonding layer includes a first outermost insulating layer providing the first outer surface, a first internal insulating layer stacked between the first outermost insulating layer and the first substrate, first external marks disposed in the first outermost insulating layer and spaced apart from each other, and first internal marks interlaced with the first external marks within the first internal insulating layer.

公开(公告)号：US20250105216A1

公开(公告)日：2025-03-27

申请号：US18808787

申请日：2024-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jing Cheng LIN ,  Youngkun Jee ,  Jihwan Suh ,  Hyunchul Jung

IPC: H01L25/065 ,  H01L23/00

Abstract: Provided is a semiconductor package and method of manufacturing same, the semiconductor package including: a first semiconductor chip; a chip stacked structure on the first semiconductor chip, the chip stacked structure including a plurality of second semiconductor chips; a third semiconductor chip on the chip stacked structure; an adhesive layer between the chip stacked structure and the third semiconductor chip; and a first pad pattern on a lower surface of the third semiconductor chip, wherein the adhesive layer surrounds the first pad pattern and the adhesive layer is between the first pad pattern and the chip stacked structure.

公开(公告)号：US20250087647A1

公开(公告)日：2025-03-13

申请号：US18818203

申请日：2024-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jing Cheng LIN ,  Youngkun Jee

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/36 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/16 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor package includes a lower redistribution structure, an internal semiconductor chip on the lower redistribution structure and including first connection pads on a lower surface of the internal semiconductor chip, conductive posts connected to the lower redistribution structure, an encapsulant surrounding a side surface of each of the conductive posts, surrounding a side surface of the internal semiconductor chip, and covering an upper surface of the internal semiconductor chip, upper trace pads on the encapsulant and respectively connected to ends of the conductive posts, an external semiconductor device on the encapsulant, the external semiconductor device including second connection pads on a lower surface of the external semiconductor device and respectively connected to the upper trace pads, and a heat dissipation structure on the encapsulant and laterally spaced apart from the external semiconductor device.

公开(公告)号：US12218102B2

公开(公告)日：2025-02-04

申请号：US17728727

申请日：2022-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngkun Jee ,  Unbyoung Kang ,  Sanghoon Lee ,  Chungsun Lee

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48

Abstract: A semiconductor package includes a first semiconductor chip including a first semiconductor substrate, and a plurality of first through electrodes penetrating at least a portion of the first semiconductor substrate. A plurality of second semiconductors include a second semiconductor substrate, the plurality of second semiconductor chips being stacked on the first semiconductor chip. A plurality of bonding pads are arranged between the first semiconductor chip and the plurality of second semiconductor chips. A chip bonding insulating layer is arranged between the first semiconductor chip and the plurality of second semiconductor chips. At least one supporting dummy substrate is stacked on the plurality of second semiconductor chips and having a support bonding insulating layer arranged on a lower surface thereof.

公开(公告)号：US20250015063A1

公开(公告)日：2025-01-09

申请号：US18655903

申请日：2024-05-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jing Cheng Lin ,  Youngkun Jee

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/48 ,  H01L23/538 ,  H01L25/065 ,  H10B80/00

Abstract: Provided is a semiconductor package including a redistribution substrate, a first semiconductor chip on the redistribution substrate, a second semiconductor chip on the redistribution substrate and spaced apart from the first semiconductor chip in a horizontal direction, a third semiconductor chip on the second semiconductor chip, and a heat dissipation chip on the first semiconductor chip and spaced apart from the third semiconductor chip in the horizontal direction, wherein the second semiconductor chip includes a plurality of through vias passing through at least a portion of the second semiconductor chip in a vertical direction, and wherein a metal pad and an adhesive layer are between the first semiconductor chip and the heat dissipation chip.