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    PCB ASSEBLY STRUCTURE FOR ELECTRONIC APPLIANCE
    11.
    发明申请
    PCB ASSEBLY STRUCTURE FOR ELECTRONIC APPLIANCE 有权

    公开(公告)号：US20210204425A1

    公开(公告)日：2021-07-01

    申请号：US16941008

    申请日：2020-07-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ho-Kweon Song ,  Hyunkyu Park ,  Eunbi Kang ,  Minsik Kim ,  Taeyoun Yoon ,  Dongjin Lee ,  Junsu Jung

    IPC: H05K5/02 ,  H05K1/02 ,  H05K5/00

    Abstract: A PCB assembly includes a panel including at least one guide protrusion, at least one mounting portion, and at least one dislocation prevention protrusion, and a PCB including at least one guide hole formed to correspond to the at least one guide protrusion, at least one grounding portion formed to correspond to the at least one mounting portion, and at least one dislocation prevention hole formed to correspond to the at least one dislocation prevention protrusion, wherein the PCB is guided to slide by the at least one guide protrusion and the at least one guide hole, is brought into close contact with the panel by the at least one mounting portion and the at least one grounding portion, and fixed to the panel as the at least one dislocation prevention hole is supported by the at least one dislocation prevention protrusion.

    SEMICONDUCTOR DEVICES INCLUDING BIT LINES
    12.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING BIT LINES 有权

    公开(公告)号：US20250107073A1

    公开(公告)日：2025-03-27

    申请号：US18804605

    申请日：2024-08-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seran Oh ,  Yunho Kang ,  Minsik Kim ,  Yeonuk Kim ,  Byounghoon Lee ,  Jangeun Lee

    IPC: H10B12/00 ,  H01L23/528 ,  H01L23/532

    Abstract: A semiconductor device may include a substrate including a first active region defined by a first device isolation layer, a bit line contact arranged on the first active region of the substrate, and a bit line that extends in a first direction on the substrate. The bit line includes a lower conductive layer arranged on the substrate and on a sidewall of the bit line contact and a metal line stack arranged on the lower conductive layer. The metal line stack includes a first conductive layer arranged on the lower conductive layer and the bit line contact and including a first metal material, a first intermediate layer arranged on the first conductive layer and including graphene, and a second conductive layer arranged on the first intermediate layer and including the first metal material.

    Display driving circuit
    14.
    发明授权
    Display driving circuit 有权

    公开(公告)号：US11817067B2

    公开(公告)日：2023-11-14

    申请号：US17221461

    申请日：2021-04-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Unki Park ,  Minsik Kim ,  Hyeonsu Park ,  Jonghyuk Lee ,  Hyunwook Lim ,  Woohyuk Jang

    IPC: G09G5/393 ,  G09G5/395 ,  G04G9/00

    CPC classification number: G09G5/393 ,  G04G9/0082 ,  G09G5/395 ,  G09G2330/023 ,  G09G2360/06

    Abstract: A display driving circuit for driving a display panel, including a first memory configured to store main image data received from outside of the display driving circuit; a second memory configured to store first additional image data in a normal mode, and to store second additional image data in an Always On Display (AOD) mode having lower power consumption than the normal mode; a normal mode controller configured to operate in the normal mode according to the first additional image data stored in the second memory; and an AOD mode controller configured to operate in the AOD mode according to the main image data stored in the first memory and the second additional image data stored in the second memory.

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